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| author |   Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> | 2018-08-10 23:23:36 +0530 |
|---|---|---|
| committer |   Wei Xu <xuwei5@hisilicon.com> | 2018-09-19 16:13:14 +0100 |
| commit | d84207999d216f743c7c011874e0a99282c64d11 (patch) | |
| tree | 4c26940b12421bc0948bbf2424573a939a0bd35a /tools/perf/scripts/python/stackcollapse.py | |
| parent | arm64: dts: hi6220: Update coresight bindings for hardware ports (diff) | |
| download | wireguard-linux-d84207999d216f743c7c011874e0a99282c64d11.tar.xz wireguard-linux-d84207999d216f743c7c011874e0a99282c64d11.zip | |
dt-bindings: arm: hisilicon: Add binding for Hi3670 SoC
Add devicetree binding for Hi3670 SoC.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions