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| author |   Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> | 2018-08-10 23:23:37 +0530 |
|---|---|---|
| committer |   Wei Xu <xuwei5@hisilicon.com> | 2018-09-19 16:14:36 +0100 |
| commit | dd8c7b78c11bac66083ec2ff0d5d7285f001cbf6 (patch) | |
| tree | d6a946907ed6d562b2e85000405c6dadd6f1819a /tools/perf/scripts/python/stackcollapse.py | |
| parent | dt-bindings: arm: hisilicon: Add binding for Hi3670 SoC (diff) | |
| download | wireguard-linux-dd8c7b78c11bac66083ec2ff0d5d7285f001cbf6.tar.xz wireguard-linux-dd8c7b78c11bac66083ec2ff0d5d7285f001cbf6.zip | |
arm64: dts: Add devicetree for Hisilicon Hi3670 SoC
Add initial devicetree support for Hisilicon Hi3670 SoC which
is similar to Hi3660 SoC with NPU support.
This SoC has Octal core BigLittle CPUs in two clusters(4 * A53 & 4 * A73).
Only UART6 has been added for console support which is
pre configured by the bootloader. A fixed clock is sourcing
the UART6 which will get replaced by the clock driver when available.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions