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| author |   Heiko Stuebner <heiko@sntech.de> | 2015-12-14 11:32:28 +0100 |
|---|---|---|
| committer | Heiko Stuebner <heiko@sntech.de> | 2016-04-06 16:25:52 -0700 |
| commit | dfb2146efc6b07f1a6cc04938248c2ce948c9c98 (patch) | |
| tree | 42511deeefc69a87766f711604a9d23db966324e /tools/perf/scripts/python/stackcollapse.py | |
| parent | ARM: dts: rockchip: add startup delay to rk3288-veyron panel-regulators (diff) | |
| download | wireguard-linux-dfb2146efc6b07f1a6cc04938248c2ce948c9c98.tar.xz wireguard-linux-dfb2146efc6b07f1a6cc04938248c2ce948c9c98.zip | |
ARM: dts: rockchip: add core rk3288-veyron backlight and panel nodes
Many Veyron chromebooks share the same panel type, so define the core
settings for all of them and allow the few runaways to override it later.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Douglas Anderson <dianders@chromium.org>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
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