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| author |   Marcus Cooper <codekipper@gmail.com> | 2017-08-19 14:48:34 +0200 |
|---|---|---|
| committer |   Mark Brown <broonie@kernel.org> | 2017-08-21 17:15:53 +0100 |
| commit | 296935213feb7bcb72ab8750a8cacb66baeb0eb3 (patch) | |
| tree | 4622eca237ba9fbe6a1a1f9fcd1814489d6b8258 /tools/perf/scripts/python/stackcollapse.py | |
| parent | ASoC: sun4i-i2s: Add regfields for word size select and sample resolution (diff) | |
| download | wireguard-linux-296935213feb7bcb72ab8750a8cacb66baeb0eb3.tar.xz wireguard-linux-296935213feb7bcb72ab8750a8cacb66baeb0eb3.zip | |
ASoC: sun4i-i2s: bclk and lrclk polarity tidyup
On newer SoCs the bit fields for the blck and lrclk polarity are in
a different locations. Use regmap fields to set the polarity bits
as intended.
Signed-off-by: Marcus Cooper <codekipper@gmail.com>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions