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| author |   Yan-Hsuan Chuang <yhchuang@realtek.com> | 2020-03-12 16:08:51 +0800 |
|---|---|---|
| committer |   Kalle Valo <kvalo@codeaurora.org> | 2020-03-23 19:29:50 +0200 |
| commit | a5697a65ecd109ce7f8e3661b89a5dffae73b512 (patch) | |
| tree | ece088a5134528f8065a593830f6645d3f4545a4 /tools/perf/scripts/python/stackcollapse.py | |
| parent | rtw88: associate reserved pages with each vif (diff) | |
| download | wireguard-linux-a5697a65ecd109ce7f8e3661b89a5dffae73b512.tar.xz wireguard-linux-a5697a65ecd109ce7f8e3661b89a5dffae73b512.zip | |
rtw88: pci: define a mask for TX/RX BD indexes
Add a macro TRX_BD_IDX_MASK for access the TX/RX BD indexes.
The hardware has only 12 bits for TX/RX BD indexes, we should not
initialize a TX/RX ring or access the TX/RX BD index with a length
that is larger than TRX_BD_IDX_MASK.
Signed-off-by: Yan-Hsuan Chuang <yhchuang@realtek.com>
Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
Link: https://lore.kernel.org/r/20200312080852.16684-5-yhchuang@realtek.com
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions