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| author |   Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> | 2016-07-23 21:10:31 +0300 |
|---|---|---|
| committer |   Simon Horman <horms+renesas@verge.net.au> | 2016-08-09 14:34:38 +0200 |
| commit | fe683922cb436097ac5b1f65148fa0db3a6735a3 (patch) | |
| tree | 4f0136a1046be81e3017ab4023073bdcf1d0d27a /tools/perf/scripts/python/stackcollapse.py | |
| parent | ARM: dts: r8a7794: Correct SDHI register size (diff) | |
| download | wireguard-linux-fe683922cb436097ac5b1f65148fa0db3a6735a3.tar.xz wireguard-linux-fe683922cb436097ac5b1f65148fa0db3a6735a3.zip | |
ARM: dts: r8a7792: add SD clocks
Describe the SDHI0 clock and its parent, SD clock in the R8A7792 device tree.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions