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| author |   Zhenyu Wang <zhenyuw@linux.intel.com> | 2010-08-27 11:08:57 +0800 |
|---|---|---|
| committer |   Chris Wilson <chris@chris-wilson.co.uk> | 2010-09-07 11:16:43 +0100 |
| commit | f8f235e5bbf4e61f3e0886a44afb1dc4cfe8f337 (patch) | |
| tree | 9211554f0542ce636aa1f14ffe58cfa832efa04d /tools/perf/scripts/python/syscall-counts-by-pid.py | |
| parent | agp/intel: use #ifdef idiom for intel-agp.h (diff) | |
| download | wireguard-linux-f8f235e5bbf4e61f3e0886a44afb1dc4cfe8f337.tar.xz wireguard-linux-f8f235e5bbf4e61f3e0886a44afb1dc4cfe8f337.zip | |
agp/intel: Fix cache control for Sandybridge
Sandybridge GTT has new cache control bits in PTE, which controls
graphics page cache in LLC or LLC/MLC, so we need to extend the mask
function to respect the new bits.
And set cache control to always LLC only by default on Gen6.
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Cc: stable@kernel.org
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Diffstat (limited to 'tools/perf/scripts/python/syscall-counts-by-pid.py')
0 files changed, 0 insertions, 0 deletions