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| author |   Haojian Zhuang <haojian.zhuang@gmail.com> | 2013-12-11 13:07:55 +0800 |
|---|---|---|
| committer | Haojian Zhuang <haojian.zhuang@gmail.com> | 2013-12-11 16:42:23 +0800 |
| commit | ea010e5188dab61b64c1ad0221adc271039e7775 (patch) | |
| tree | 88f3aaf6122d5d8acf0eb50b3839a84f62fe62ba /tools/perf/scripts/python/syscall-counts.py | |
| parent | clk: hi3620: fix wrong flags on divider (diff) | |
| download | wireguard-linux-ea010e5188dab61b64c1ad0221adc271039e7775.tar.xz wireguard-linux-ea010e5188dab61b64c1ad0221adc271039e7775.zip | |
clk: hi3620: add gate clock flag
Add missing CLK_SET_RATE_PARENT flag for gate clock.
Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>
Diffstat (limited to '')
0 files changed, 0 insertions, 0 deletions