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| author |   Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> | 2017-04-15 23:18:28 +0300 |
|---|---|---|
| committer |   Simon Horman <horms+renesas@verge.net.au> | 2017-08-15 18:00:17 +0200 |
| commit | 485a40469cf05d7948e1d8c9dbd9058044ded91c (patch) | |
| tree | d0149f91334d66fdb1199807ec9206019babcb09 /tools/perf/scripts/python/syscall-counts.py | |
| parent | ARM: dts: sk-rzg1e: add SCIF2 pins (diff) | |
| download | wireguard-linux-485a40469cf05d7948e1d8c9dbd9058044ded91c.tar.xz wireguard-linux-485a40469cf05d7948e1d8c9dbd9058044ded91c.zip | |
ARM: dts: sk-rzg1e: add Ether pins
Add the (previously omitted) Ether/PHY pin data to the SK-RZG1E board's
device tree.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'tools/perf/scripts/python/syscall-counts.py')
0 files changed, 0 insertions, 0 deletions