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| author |   Geert Uytterhoeven <geert+renesas@glider.be> | 2024-11-03 12:29:40 +0100 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2024-11-03 12:29:40 +0100 |
| commit | 75f3dec9a4d971ae71a491229340a0911e9c23f6 (patch) | |
| tree | b2040b3e46be3c2e4293d118630472a8f26a6050 /tools/perf/scripts/python/syscall-counts.py | |
| parent | arm64: dts: renesas: white-hawk-cpu-common: Add pin control for DSI-eDP IRQ (diff) | |
| parent | dt-bindings: clock: renesas,r9a08g045-vbattb: Document VBATTB (diff) | |
| download | wireguard-linux-75f3dec9a4d971ae71a491229340a0911e9c23f6.tar.xz wireguard-linux-75f3dec9a4d971ae71a491229340a0911e9c23f6.zip | |
Merge tag 'renesas-r9a08g045-dt-binding-defs-tag3' into renesas-dts-for-v6.13
Renesas RZ/G3S DT Binding Definitions
VBATTB clock definitions for the Renesas RZ/G3S (R9A08G045) SoC, shared
by driver and DT source files.
Diffstat (limited to 'tools/perf/scripts/python/syscall-counts.py')
0 files changed, 0 insertions, 0 deletions