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| author |   Ben Skeggs <bskeggs@redhat.com> | 2011-10-07 16:00:31 +1000 |
|---|---|---|
| committer | Ben Skeggs <bskeggs@redhat.com> | 2011-11-10 08:58:47 +1000 |
| commit | 7b4b98fa0c4d3a975b36bfe9984e4cd117f2ddff (patch) | |
| tree | 1bbc4e238e4f69001c63b75476485db6deffffa7 /tools/perf/scripts/python/syscall-counts.py | |
| parent | drm/nv50/gr: typo fix, how about we not reset fifo during graph init? (diff) | |
| download | wireguard-linux-7b4b98fa0c4d3a975b36bfe9984e4cd117f2ddff.tar.xz wireguard-linux-7b4b98fa0c4d3a975b36bfe9984e4cd117f2ddff.zip | |
drm/nv50/vram: fix incorrect detection of bank count on newer chipsets
NVA3+ has an extra bit here compared to NV50:NVA3 chipsets.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'tools/perf/scripts/python/syscall-counts.py')
0 files changed, 0 insertions, 0 deletions