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| author |   Thierry Reding <treding@nvidia.com> | 2014-06-05 16:19:48 +0200 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2014-06-09 12:02:50 +0200 |
| commit | 899451b787eb55d51c46468aaf99367c5f3420a1 (patch) | |
| tree | 4985096378aa5bc6fcf90f68543565ec07fe9fbd /tools/perf/scripts/python/syscall-counts.py | |
| parent | drm/tegra: sor - Do not program interlaced mode registers (diff) | |
| download | wireguard-linux-899451b787eb55d51c46468aaf99367c5f3420a1.tar.xz wireguard-linux-899451b787eb55d51c46468aaf99367c5f3420a1.zip | |
drm/tegra: sor - Power on only the necessary lanes
Power on only those lanes required for the specified link.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'tools/perf/scripts/python/syscall-counts.py')
0 files changed, 0 insertions, 0 deletions