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author | 2024-10-23 12:17:34 +0300 | |
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committer | 2024-10-26 14:08:56 +0200 | |
commit | a5541d737c8de71948bcdaee912bcb6b0781af7e (patch) | |
tree | 8f9e750dc4d6d29bf2b789fd5c0bb18f6983c751 /tools/perf/scripts/python/syscall-counts.py | |
parent | arm64: dts: exynos8895: Add Multi Core Timer (MCT) node (diff) | |
download | wireguard-linux-a5541d737c8de71948bcdaee912bcb6b0781af7e.tar.xz wireguard-linux-a5541d737c8de71948bcdaee912bcb6b0781af7e.zip |
arm64: dts: exynos8895: Add spi_0/1 nodes
Add nodes for spi_0 (SPI_CAM0) and spi_1 (SPI_CAM1), which
allows using them.
Signed-off-by: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com>
Link: https://lore.kernel.org/r/20241023091734.538682-6-ivo.ivanov.ivanov1@gmail.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Diffstat (limited to 'tools/perf/scripts/python/syscall-counts.py')
0 files changed, 0 insertions, 0 deletions