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| author |   Christian Glindkamp <christian.glindkamp@taskit.de> | 2010-12-09 11:15:59 +0100 |
|---|---|---|
| committer |   Nicolas Ferre <nicolas.ferre@atmel.com> | 2010-12-17 12:10:39 +0100 |
| commit | c20b4dd31820a551d0fb60bf27b99345905c2eb6 (patch) | |
| tree | 470d233028356edf47a4a7898660e8d1e8ca2164 /tools/perf/scripts/python/syscall-counts.py | |
| parent | at91: Fix uhpck clock rate in upll case (diff) | |
| download | wireguard-linux-c20b4dd31820a551d0fb60bf27b99345905c2eb6.tar.xz wireguard-linux-c20b4dd31820a551d0fb60bf27b99345905c2eb6.zip | |
at91: Refactor Stamp9G20 and PControl G20 board file
As PControl G20 is a carrier board for the Stamp9G20 SoM, some code can
be shared. Therefore board-stamp9g20.c is refactored to allow reusing the
SoM initialization and board-pcontrol-g20.c is modified to use it.
Signed-off-by: Christian Glindkamp <christian.glindkamp@taskit.de>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Diffstat (limited to 'tools/perf/scripts/python/syscall-counts.py')
0 files changed, 0 insertions, 0 deletions