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| author |   Imran Shaik <quic_imrashai@quicinc.com> | 2023-05-12 17:53:43 +0530 |
|---|---|---|
| committer |   Bjorn Andersson <andersson@kernel.org> | 2023-05-24 21:47:17 -0700 |
| commit | 9092d1083a6253757c7f9449340173443c81768c (patch) | |
| tree | 3090419f961313acae68d3c871a0284e8e8da0a9 /tools/perf/scripts/python | |
| parent | Merge branch '20230512122347.1219-3-quic_tdas@quicinc.com' into clk-for-6.5 (diff) | |
| download | wireguard-linux-9092d1083a6253757c7f9449340173443c81768c.tar.xz wireguard-linux-9092d1083a6253757c7f9449340173443c81768c.zip | |
clk: qcom: branch: Extend the invert logic for branch2 clocks
Add support to handle the invert logic for branch2 clocks.
Invert branch halt would indicate the clock ON when CLK_OFF
bit is '1' and OFF when CLK_OFF bit is '0'.
Signed-off-by: Imran Shaik <quic_imrashai@quicinc.com>
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230512122347.1219-2-quic_tdas@quicinc.com
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions