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| author |   Jagadeesh Kona <quic_jkona@quicinc.com> | 2023-05-24 20:22:01 +0530 |
|---|---|---|
| committer |   Bjorn Andersson <andersson@kernel.org> | 2023-05-24 21:47:16 -0700 |
| commit | c7d91f26f0f70f03a09bb6cdbfa1b7df28ab121e (patch) | |
| tree | f29a7a2f59de506ed132903d219b7f70f77beb76 /tools/perf/scripts/python | |
| parent | clk: qcom: clk-alpha-pll: Add support to configure PLL_TEST_CTL_U2 (diff) | |
| download | wireguard-linux-c7d91f26f0f70f03a09bb6cdbfa1b7df28ab121e.tar.xz wireguard-linux-c7d91f26f0f70f03a09bb6cdbfa1b7df28ab121e.zip | |
dt-bindings: clock: qcom: Add SM8550 video clock controller
Add compatible string for SM8550 video clock controller.
Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230524145203.13153-3-quic_jkona@quicinc.com
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions