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| author |   Daniel Palmer <daniel@0x0f.com> | 2021-02-23 15:18:23 +0900 |
|---|---|---|
| committer |   Romain Perier <romain.perier@gmail.com> | 2022-02-16 19:16:03 +0100 |
| commit | c952e5075de1f76e092bc780503ebc5cb8222a01 (patch) | |
| tree | dfba76087a292a3e1e7d5ae5488c7acb7e6b4798 /tools/perf/scripts/python | |
| parent | ARM: dts: mstar: Add board for 100ask DongShanPiOne (diff) | |
| download | wireguard-linux-c952e5075de1f76e092bc780503ebc5cb8222a01.tar.xz wireguard-linux-c952e5075de1f76e092bc780503ebc5cb8222a01.zip | |
dt-bindings: clk: mstar msc313 cpupll binding description
Add a binding description for the MStar/SigmaStar CPU PLL block.
Signed-off-by: Daniel Palmer <daniel@0x0f.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions