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| author |   Clemens Ladisch <clemens@ladisch.de> | 2011-01-10 16:09:23 +0100 |
|---|---|---|
| committer |   Takashi Iwai <tiwai@suse.de> | 2011-01-10 16:46:21 +0100 |
| commit | 00b8dd7dd71ef129176731d5fa24f5e298797599 (patch) | |
| tree | a3cb8cef9a89f6a0b55490adab58ae257a05a294 /tools/perf/util/scripting-engines/trace-event-python.c | |
| parent | ALSA: virtuoso: configure correct master clock frequency on the CS2000 (diff) | |
| download | wireguard-linux-00b8dd7dd71ef129176731d5fa24f5e298797599.tar.xz wireguard-linux-00b8dd7dd71ef129176731d5fa24f5e298797599.zip | |
ALSA: virtuoso: use lower master clock with H6 daughterboard
Because of the unshielded connector cable, it is important to use as low
a master clock frequency as possible with the H6.
For double rate modes (64-96 kHz), the MCLK rate is unconditionally
lowered from 512x to 256x because the higher rate would not improve
anything.
Signed-off-by: Clemens Ladisch <clemens@ladisch.de>
Signed-off-by: Takashi Iwai <tiwai@suse.de>
Diffstat (limited to 'tools/perf/util/scripting-engines/trace-event-python.c')
0 files changed, 0 insertions, 0 deletions