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| author |   Kyungmin Park <kyungmin.park@samsung.com> | 2010-10-21 15:22:36 +0900 |
|---|---|---|
| committer |   Kukjin Kim <kgene.kim@samsung.com> | 2010-10-25 16:11:16 +0900 |
| commit | 1cf0eb799759b24199374955976fee8469835203 (patch) | |
| tree | 744cd0ca71a58f1e0dc9807c44e648ede6f70fe2 /tools/perf/util/scripting-engines/trace-event-python.c | |
| parent | ARM: S5PV310: Remove L2 cache init in machine (diff) | |
| download | wireguard-linux-1cf0eb799759b24199374955976fee8469835203.tar.xz wireguard-linux-1cf0eb799759b24199374955976fee8469835203.zip | |
ARM: S5PV310: Add L2 cache init function in cpu.c
This patch adds L2 cache initialization code in cpu.c of ARCH_S5PV310.
It includes TAG and Data latency, Prefetch, and Power configurations.
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Changhwan Youn <chaos.youn@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'tools/perf/util/scripting-engines/trace-event-python.c')
0 files changed, 0 insertions, 0 deletions