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| author |   Mike Frysinger <vapier@gentoo.org> | 2010-10-27 10:06:32 -0400 |
|---|---|---|
| committer | Mike Frysinger <vapier@gentoo.org> | 2011-01-10 07:18:10 -0500 |
| commit | 94a038c2e6228727ae0549af75e97b9b634cd468 (patch) | |
| tree | 2428073e580a236b3324e1459105d8a8f2498f34 /tools/perf/util/scripting-engines/trace-event-python.c | |
| parent | Blackfin: drop asm/irq.h include from mach headers (diff) | |
| download | wireguard-linux-94a038c2e6228727ae0549af75e97b9b634cd468.tar.xz wireguard-linux-94a038c2e6228727ae0549af75e97b9b634cd468.zip | |
Blackfin: bf561: update a few more SIC_SYSCR locations
Looks like I missed a few new spots when renaming the SICA macros.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat (limited to 'tools/perf/util/scripting-engines/trace-event-python.c')
0 files changed, 0 insertions, 0 deletions