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| author |   Akinobu Mita <akinobu.mita@gmail.com> | 2011-01-20 20:32:14 +0900 |
|---|---|---|
| committer |   Ingo Molnar <mingo@elte.hu> | 2011-01-21 14:11:12 +0100 |
| commit | cc67ba6352ecbf6891083a18f8c78fa639ebd274 (patch) | |
| tree | 728c4783f72b50cc8ef7b1af62c7e376efe409d6 /tools/perf/util/scripting-engines/trace-event-python.c | |
| parent | x86: Update CPU cache attributes table descriptors (diff) | |
| download | wireguard-linux-cc67ba6352ecbf6891083a18f8c78fa639ebd274.tar.xz wireguard-linux-cc67ba6352ecbf6891083a18f8c78fa639ebd274.zip | |
x86: Use asm-generic/cacheflush.h
The implementation of the cache flushing interfaces on the x86
is identical with the default implementation in asm-generic.
Signed-off-by: Akinobu Mita <akinobu.mita@gmail.com>
Cc: "H. Peter Anvin" <hpa@zytor.com>
Cc: arnd@arndb.de
LKML-Reference: <1295523136-4277-2-git-send-email-akinobu.mita@gmail.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'tools/perf/util/scripting-engines/trace-event-python.c')
0 files changed, 0 insertions, 0 deletions