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| author |   Jon Mason <jon.mason@broadcom.com> | 2017-03-02 19:21:32 -0500 |
|---|---|---|
| committer |   Florian Fainelli <f.fainelli@gmail.com> | 2017-03-05 17:10:55 -0800 |
| commit | 0c2bf9f95983fe30aa2f6463cb761cd42c2d521a (patch) | |
| tree | f3625cea02f6a8e9af1d2ec1afb745df520c8040 /tools/perf/util/scripting-engines/trace-event-python.c | |
| parent | ARM: dts: BCM5301X: Fix memory start address (diff) | |
| download | wireguard-linux-0c2bf9f95983fe30aa2f6463cb761cd42c2d521a.tar.xz wireguard-linux-0c2bf9f95983fe30aa2f6463cb761cd42c2d521a.zip | |
ARM: dts: BCM5301X: Correct GIC_PPI interrupt flags
GIC_PPI flags were misconfigured for the timers, resulting in errors
like:
[ 0.000000] GIC: PPI11 is secure or misconfigured
Changing them to being edge triggered corrects the issue
Suggested-by: Rafał Miłecki <rafal@milecki.pl>
Signed-off-by: Jon Mason <jon.mason@broadcom.com>
Fixes: d27509f1 ("ARM: BCM5301X: add dts files for BCM4708 SoC")
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Diffstat (limited to 'tools/perf/util/scripting-engines/trace-event-python.c')
0 files changed, 0 insertions, 0 deletions