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| author |   Marc Zyngier <marc.zyngier@arm.com> | 2013-06-21 13:08:47 +0100 |
|---|---|---|
| committer |   Christoffer Dall <christoffer.dall@linaro.org> | 2013-06-26 10:50:04 -0700 |
| commit | 479c5ae2f8a55509b691494cd13691d3dc31d102 (patch) | |
| tree | 6892951511aa62357eec0266f1dc6ca1d4bc9652 /tools/perf/util/scripting-engines/trace-event-python.c | |
| parent | ARM: KVM: perform save/restore of PAR (diff) | |
| download | wireguard-linux-479c5ae2f8a55509b691494cd13691d3dc31d102.tar.xz wireguard-linux-479c5ae2f8a55509b691494cd13691d3dc31d102.zip | |
ARM: KVM: add missing dsb before invalidating Stage-2 TLBs
When performing a Stage-2 TLB invalidation, it is necessary to
make sure the write to the page tables is observable by all CPUs.
For this purpose, add a dsb instruction to __kvm_tlb_flush_vmid_ipa
before doing the TLB invalidation itself.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
Diffstat (limited to 'tools/perf/util/scripting-engines/trace-event-python.c')
0 files changed, 0 insertions, 0 deletions