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| author |   Palmer Dabbelt <palmer@rivosinc.com> | 2022-03-17 14:09:16 -0700 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@rivosinc.com> | 2022-03-17 14:09:16 -0700 |
| commit | 6b57ac02b45f7f676c81b1357e7e5d63a974bf60 (patch) | |
| tree | 1fdcd2eb0e2dd0b48102b47c27b59837fe950f70 /tools/perf/util/scripting-engines/trace-event-python.c | |
| parent | riscv: Fixed misaligned memory access. Fixed pointer comparison. (diff) | |
| parent | RISC-V: Improve /proc/cpuinfo output for ISA extensions (diff) | |
| download | wireguard-linux-6b57ac02b45f7f676c81b1357e7e5d63a974bf60.tar.xz wireguard-linux-6b57ac02b45f7f676c81b1357e7e5d63a974bf60.zip | |
RISC-V: Provide a fraemework for RISC-V ISA extensions
This series implements a generic framework to parse multi-letter ISA
extensions.
* palmer/riscv-isa:
RISC-V: Improve /proc/cpuinfo output for ISA extensions
RISC-V: Do no continue isa string parsing without correct XLEN
RISC-V: Implement multi-letter ISA extension probing framework
RISC-V: Extract multi-letter extension names from "riscv, isa"
RISC-V: Minimal parser for "riscv, isa" strings
RISC-V: Correctly print supported extensions
Diffstat (limited to 'tools/perf/util/scripting-engines/trace-event-python.c')
0 files changed, 0 insertions, 0 deletions