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| author |   Mark Rutland <mark.rutland@arm.com> | 2017-02-09 15:19:19 +0000 |
|---|---|---|
| committer |   Will Deacon <will.deacon@arm.com> | 2017-02-15 12:20:29 +0000 |
| commit | 8b6e70fccff27121430114b4507f0adfb790752f (patch) | |
| tree | 016d408b470e110bae2475374c829ecf0c0ffa89 /tools/perf/util/scripting-engines/trace-event-python.c | |
| parent | arm64: ptrace: add XZR-safe regs accessors (diff) | |
| download | wireguard-linux-8b6e70fccff27121430114b4507f0adfb790752f.tar.xz wireguard-linux-8b6e70fccff27121430114b4507f0adfb790752f.zip | |
arm64: traps: correctly handle MRS/MSR with XZR
Currently we hand-roll XZR-safe register handling in
user_cache_maint_handler(), though we forget to do the same in
ctr_read_handler(), and may erroneously write back to the user SP rather
than XZR.
Use the new helpers to handle these cases correctly and consistently.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Fixes: 116c81f427ff6c53 ("arm64: Work around systems with mismatched cache line sizes")
Cc: Andre Przywara <andre.przywara@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Diffstat (limited to 'tools/perf/util/scripting-engines/trace-event-python.c')
0 files changed, 0 insertions, 0 deletions