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| author |   Peter Ujfalusi <peter.ujfalusi@ti.com> | 2014-04-02 16:46:25 +0300 |
|---|---|---|
| committer |   Tony Lindgren <tony@atomide.com> | 2014-04-18 15:53:33 -0700 |
| commit | 8c0b4fd89ead67f5aca63abbadc81dd316b6462c (patch) | |
| tree | 130cc29dce69a8cd14f957340660b9167d7abdaf /tools/perf/util/scripting-engines/trace-event-python.c | |
| parent | ARM: dts: omap5: Add clocks to USB3 PHY node (diff) | |
| download | wireguard-linux-8c0b4fd89ead67f5aca63abbadc81dd316b6462c.tar.xz wireguard-linux-8c0b4fd89ead67f5aca63abbadc81dd316b6462c.zip | |
ARM: dts: dra7xx-clocks: Correct mcasp2_ahclkx_mux bit-shift
The correct bit is 24 for AHCLKX.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Acked-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'tools/perf/util/scripting-engines/trace-event-python.c')
0 files changed, 0 insertions, 0 deletions