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| author |   Max Filippov <jcmvbkbc@gmail.com> | 2021-12-28 01:20:20 -0800 |
|---|---|---|
| committer | Max Filippov <jcmvbkbc@gmail.com> | 2022-03-09 13:59:15 -0800 |
| commit | 8c9ab55c0fbdc76cb876140c2dad75a610bb23ef (patch) | |
| tree | fa1d77ae433a07ecef3e1afc529cd0122d5452ca /tools/perf/util/scripting-engines/trace-event-python.c | |
| parent | xtensa: use XCHAL_NUM_AREGS as pt_regs::areg size (diff) | |
| download | wireguard-linux-8c9ab55c0fbdc76cb876140c2dad75a610bb23ef.tar.xz wireguard-linux-8c9ab55c0fbdc76cb876140c2dad75a610bb23ef.zip | |
xtensa: add missing XCHAL_HAVE_WINDOWED check
Add missing preprocessor conditions to secondary reset vector code.
Fixes: 09af39f649da ("xtensa: use register window specific opcodes only when present")
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Diffstat (limited to 'tools/perf/util/scripting-engines/trace-event-python.c')
0 files changed, 0 insertions, 0 deletions