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| author |   Anson Huang <b20788@freescale.com> | 2013-05-31 17:01:54 -0400 |
|---|---|---|
| committer |   Shawn Guo <shawn.guo@linaro.org> | 2013-06-03 13:47:12 +0800 |
| commit | a08b9bc586a7810cdebbc316d5cbaed56a2a04a9 (patch) | |
| tree | 4acb676c9a07b153f3f202cd7f1d782273b5ee86 /tools/perf/util/scripting-engines/trace-event-python.c | |
| parent | ARM: dts: imx: fix clocks for cspi (diff) | |
| download | wireguard-linux-a08b9bc586a7810cdebbc316d5cbaed56a2a04a9.tar.xz wireguard-linux-a08b9bc586a7810cdebbc316d5cbaed56a2a04a9.zip | |
ARM: imx: clk-imx6q: AXI clock select index is incorrect
The AXI clock mux should be as below:
00: periph;
01: pll2_pfd2_396m;
10: periph;
11: pll3_pfd1_540m;
Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Diffstat (limited to 'tools/perf/util/scripting-engines/trace-event-python.c')
0 files changed, 0 insertions, 0 deletions