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| author |   Jörg Krause <jk@lintech.de> | 2017-01-13 21:44:27 +0100 |
|---|---|---|
| committer |   Mark Brown <broonie@kernel.org> | 2017-01-17 18:19:36 +0000 |
| commit | bcb8c270829a639b8b838809d7c2b540e65f4e01 (patch) | |
| tree | b0b0de3f797ab5efe4e3a5b6ef4ced3f9036b3d6 /tools/perf/util/scripting-engines/trace-event-python.c | |
| parent | ASoC: mxs-saif: fix setting SAIF1 register (diff) | |
| download | wireguard-linux-bcb8c270829a639b8b838809d7c2b540e65f4e01.tar.xz wireguard-linux-bcb8c270829a639b8b838809d7c2b540e65f4e01.zip | |
ASoC: mxs-saif: fix setting master base rate
The SAIF base oversample rates are either 512*fs or 384*fs. An additional
divider exists within the SAIF to generate sub-multiples of these two base
rates if MCLK is required by the codec.
* The sub-rates for the 512x base rate are: 256x, 128x, 64x, and 32x.
* The sub-rates for the 384x base rate are: 192x, 96x, and 48x.
Setting the base rate depending on the modulo operation with 32 and 48
give wrong results for some mclk.
If mclk=18.432MHz both modulo operations results in 0. As testing the
result with 32 is done first, a wrong base rate of 512*fs is set instead
of the correct 384*fs.
Fix this by setting the base rate depending on the calculated sub-rate.
Signed-off-by: Jörg Krause <joerg.krause@embedded.rocks>
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'tools/perf/util/scripting-engines/trace-event-python.c')
0 files changed, 0 insertions, 0 deletions