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| author |   Haojian Zhuang <haojian.zhuang@linaro.org> | 2013-06-08 22:47:18 +0800 |
|---|---|---|
| committer |   Mike Turquette <mturquette@linaro.org> | 2013-06-15 20:23:49 -0700 |
| commit | d57dfe7508af2b528e26d84792edec1e7d919682 (patch) | |
| tree | f3be7ce2e20cdf9fad2528b4a1972e29df20a662 /tools/perf/util/scripting-engines/trace-event-python.c | |
| parent | clk: mux: add CLK_MUX_HIWORD_MASK (diff) | |
| download | wireguard-linux-d57dfe7508af2b528e26d84792edec1e7d919682.tar.xz wireguard-linux-d57dfe7508af2b528e26d84792edec1e7d919682.zip | |
clk: divider: add CLK_DIVIDER_HIWORD_MASK flag
In both Hisilicon & Rockchip Cortex-A9 based chips, they don't use the
paradigm of reading-changing-writing the register contents.
Instead they use a hiword mask to indicate the changed bits.
When b01 should be set as setting divider, it also needs to indicate
the change by setting hiword mask (b11 << 16).
The patch adds divider flag for this usage.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Diffstat (limited to 'tools/perf/util/scripting-engines/trace-event-python.c')
0 files changed, 0 insertions, 0 deletions