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| author |   David E. Box <david.e.box@linux.intel.com> | 2017-01-19 16:25:21 +0200 |
|---|---|---|
| committer |   Mark Brown <broonie@kernel.org> | 2017-01-19 14:55:21 +0000 |
| commit | e18a80acd1365e91e3efcd69942d9073936cf851 (patch) | |
| tree | aee5281a5524c828956e6bd54e4ab9a200e607f8 /tools/perf/util/scripting-engines/trace-event-python.c | |
| parent | spi: pxa2xx: add missed break (diff) | |
| download | wireguard-linux-e18a80acd1365e91e3efcd69942d9073936cf851.tar.xz wireguard-linux-e18a80acd1365e91e3efcd69942d9073936cf851.zip | |
spi: pxa2xx: Add support for Intel Gemini Lake
Gemini Lake reuses the same LPSS SPI configuration as Broxton
Signed-off-by: David E. Box <david.e.box@linux.intel.com>
Signed-off-by: Jarkko Nikula <jarkko.nikula@linux.intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'tools/perf/util/scripting-engines/trace-event-python.c')
0 files changed, 0 insertions, 0 deletions