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| author |   Geert Uytterhoeven <geert+renesas@glider.be> | 2017-10-12 11:35:16 +0200 |
|---|---|---|
| committer |   Simon Horman <horms+renesas@verge.net.au> | 2017-10-16 11:43:49 +0200 |
| commit | e5042d0b97be6a831f9f204f3574d73b3f947fa5 (patch) | |
| tree | 95e3070246e08f424efb8bc4f8b3594f800e6f57 /tools/perf/util/scripting-engines/trace-event-python.c | |
| parent | ARM: dts: r8a7794: Add missing clock for secondary CA7 CPU core (diff) | |
| download | wireguard-linux-e5042d0b97be6a831f9f204f3574d73b3f947fa5.tar.xz wireguard-linux-e5042d0b97be6a831f9f204f3574d73b3f947fa5.zip | |
ARM: dts: sh73a0: Add clocks for CA9 CPU cores
Improve hardware description by adding clocks properties to the device
nodes corresponding to the CA9 CPU cores.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'tools/perf/util/scripting-engines/trace-event-python.c')
0 files changed, 0 insertions, 0 deletions