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| author |   Geert Uytterhoeven <geert+renesas@glider.be> | 2017-10-12 11:35:14 +0200 |
|---|---|---|
| committer |   Simon Horman <horms+renesas@verge.net.au> | 2017-10-16 11:43:06 +0200 |
| commit | f359fd3bba71176a122939fe3db9c7f20000d3f0 (patch) | |
| tree | dc9a953580877df7329ff58383869d7e05091815 /tools/perf/util/scripting-engines/trace-event-python.c | |
| parent | ARM: dts: r8a7792: Add missing clock for secondary CA15 CPU core (diff) | |
| download | wireguard-linux-f359fd3bba71176a122939fe3db9c7f20000d3f0.tar.xz wireguard-linux-f359fd3bba71176a122939fe3db9c7f20000d3f0.zip | |
ARM: dts: r8a7793: Add missing clock for secondary CA15 CPU core
Currently only the primary CPU in the CA15 cluster has a clocks
property, while the secondary CPU core is driven by the same clock.
Add the missing clocks property to fix this.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'tools/perf/util/scripting-engines/trace-event-python.c')
0 files changed, 0 insertions, 0 deletions