diff options
Diffstat (limited to '')
25 files changed, 1644 insertions, 113 deletions
diff --git a/Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml b/Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml index 926c503bed1f..c3fe76abd549 100644 --- a/Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml +++ b/Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml @@ -4,19 +4,22 @@ $id: http://devicetree.org/schemas/clock/renesas,rzv2h-cpg.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Renesas RZ/V2H(P) Clock Pulse Generator (CPG) +title: Renesas RZ/{G3E,V2H(P)} Clock Pulse Generator (CPG) maintainers: - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> description: - On Renesas RZ/V2H(P) SoCs, the CPG (Clock Pulse Generator) handles generation - and control of clock signals for the IP modules, generation and control of resets, - and control over booting, low power consumption and power supply domains. + On Renesas RZ/{G3E,V2H(P)} SoCs, the CPG (Clock Pulse Generator) handles + generation and control of clock signals for the IP modules, generation and + control of resets, and control over booting, low power consumption and power + supply domains. properties: compatible: - const: renesas,r9a09g057-cpg + enum: + - renesas,r9a09g047-cpg # RZ/G3E + - renesas,r9a09g057-cpg # RZ/V2H reg: maxItems: 1 @@ -37,7 +40,7 @@ properties: description: | - For CPG core clocks, the two clock specifier cells must be "CPG_CORE" and a core clock reference, as defined in - <dt-bindings/clock/renesas,r9a09g057-cpg.h>, + <dt-bindings/clock/renesas,r9a09g0*-cpg.h>, - For module clocks, the two clock specifier cells must be "CPG_MOD" and a module number. The module number is calculated as the CLKON register offset index multiplied by 16, plus the actual bit in the register diff --git a/Documentation/devicetree/bindings/soc/renesas/renesas.yaml b/Documentation/devicetree/bindings/soc/renesas/renesas.yaml index b7acb65bdecd..225c0f07ae94 100644 --- a/Documentation/devicetree/bindings/soc/renesas/renesas.yaml +++ b/Documentation/devicetree/bindings/soc/renesas/renesas.yaml @@ -360,19 +360,21 @@ properties: - renesas,white-hawk-cpu # White Hawk CPU board (RTP8A779G0ASKB0FC0SA000) - const: renesas,r8a779g0 - - description: R-Car V4H (R8A779G2) - items: - - enum: - - renesas,white-hawk-single # White Hawk Single board (RTP8A779G2ASKB0F10SA001) - - const: renesas,r8a779g2 - - const: renesas,r8a779g0 - - items: - enum: - renesas,white-hawk-breakout # White Hawk BreakOut board (RTP8A779G0ASKB0SB0SA000) - const: renesas,white-hawk-cpu - const: renesas,r8a779g0 + - description: R-Car V4H (R8A779G[23]) + items: + - enum: + - renesas,white-hawk-single # White Hawk Single board (RTP8A779G[23]ASKB0F10SA001) + - enum: + - renesas,r8a779g2 # ES2.x + - renesas,r8a779g3 # ES3.x + - const: renesas,r8a779g0 + - description: R-Car V4M (R8A779H0) items: - enum: @@ -525,6 +527,23 @@ properties: - renesas,rzv2mevk2 # RZ/V2M Eval Board v2.0 - const: renesas,r9a09g011 + - description: RZ/G3E (R9A09G047) + items: + - enum: + - renesas,smarc2-evk # RZ SMARC Carrier-II EVK + - enum: + - renesas,rzg3e-smarcm # RZ/G3E SMARC Module (SoM) + - enum: + - renesas,r9a09g047e27 # Dual Cortex-A55 + Cortex-M33 (15mm BGA) + - renesas,r9a09g047e28 # Dual Cortex-A55 + Cortex-M33 (21mm BGA) + - renesas,r9a09g047e37 # Dual Cortex-A55 + Cortex-M33 + Ethos-U55 (15mm BGA) + - renesas,r9a09g047e38 # Dual Cortex-A55 + Cortex-M33 + Ethos-U55 (21mm BGA) + - renesas,r9a09g047e47 # Quad Cortex-A55 + Cortex-M33 (15mm BGA) + - renesas,r9a09g047e48 # Quad Cortex-A55 + Cortex-M33 (21mm BGA) + - renesas,r9a09g047e57 # Quad Cortex-A55 + Cortex-M33 + Ethos-U55 (15mm BGA) + - renesas,r9a09g047e58 # Quad Cortex-A55 + Cortex-M33 + Ethos-U55 (21mm BGA) + - const: renesas,r9a09g047 + - description: RZ/V2H(P) (R9A09G057) items: - enum: diff --git a/arch/arm/boot/dts/renesas/r7s72100.dtsi b/arch/arm/boot/dts/renesas/r7s72100.dtsi index b831bbc431ef..1a866dbaf5e9 100644 --- a/arch/arm/boot/dts/renesas/r7s72100.dtsi +++ b/arch/arm/boot/dts/renesas/r7s72100.dtsi @@ -238,6 +238,8 @@ <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "error", "rx", "tx"; clocks = <&mstp10_clks R7S72100_CLK_SPI0>; + dmas = <&dmac 0x2d21>, <&dmac 0x2d22>; + dma-names = "tx", "rx"; power-domains = <&cpg_clocks>; num-cs = <1>; #address-cells = <1>; @@ -253,6 +255,8 @@ <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "error", "rx", "tx"; clocks = <&mstp10_clks R7S72100_CLK_SPI1>; + dmas = <&dmac 0x2d25>, <&dmac 0x2d26>; + dma-names = "tx", "rx"; power-domains = <&cpg_clocks>; num-cs = <1>; #address-cells = <1>; @@ -268,6 +272,8 @@ <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "error", "rx", "tx"; clocks = <&mstp10_clks R7S72100_CLK_SPI2>; + dmas = <&dmac 0x2d29>, <&dmac 0x2d2a>; + dma-names = "tx", "rx"; power-domains = <&cpg_clocks>; num-cs = <1>; #address-cells = <1>; @@ -283,6 +289,8 @@ <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "error", "rx", "tx"; clocks = <&mstp10_clks R7S72100_CLK_SPI3>; + dmas = <&dmac 0x2d2d>, <&dmac 0x2d2e>; + dma-names = "tx", "rx"; power-domains = <&cpg_clocks>; num-cs = <1>; #address-cells = <1>; @@ -298,6 +306,8 @@ <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "error", "rx", "tx"; clocks = <&mstp10_clks R7S72100_CLK_SPI4>; + dmas = <&dmac 0x2d31>, <&dmac 0x2d32>; + dma-names = "tx", "rx"; power-domains = <&cpg_clocks>; num-cs = <1>; #address-cells = <1>; diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile index 97228a3cb99c..928635f2e76b 100644 --- a/arch/arm64/boot/dts/renesas/Makefile +++ b/arch/arm64/boot/dts/renesas/Makefile @@ -86,11 +86,17 @@ dtb-$(CONFIG_ARCH_R8A779F0) += r8a779f4-s4sk.dtb dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g0-white-hawk.dtb dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g0-white-hawk-cpu.dtb -dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g0-white-hawk-ard-audio-da7212.dtbo -r8a779g0-white-hawk-ard-audio-da7212-dtbs := r8a779g0-white-hawk.dtb r8a779g0-white-hawk-ard-audio-da7212.dtbo +dtb-$(CONFIG_ARCH_R8A779G0) += white-hawk-ard-audio-da7212.dtbo +r8a779g0-white-hawk-ard-audio-da7212-dtbs := r8a779g0-white-hawk.dtb white-hawk-ard-audio-da7212.dtbo dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g0-white-hawk-ard-audio-da7212.dtb dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g2-white-hawk-single.dtb +r8a779g2-white-hawk-single-ard-audio-da7212-dtbs := r8a779g2-white-hawk-single.dtb white-hawk-ard-audio-da7212.dtbo +dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g2-white-hawk-single-ard-audio-da7212.dtb + +dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g3-white-hawk-single.dtb +r8a779g3-white-hawk-single-ard-audio-da7212-dtbs := r8a779g3-white-hawk-single.dtb white-hawk-ard-audio-da7212.dtbo +dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g3-white-hawk-single-ard-audio-da7212.dtb dtb-$(CONFIG_ARCH_R8A779H0) += r8a779h0-gray-hawk-single.dtb @@ -140,6 +146,8 @@ dtb-$(CONFIG_ARCH_R9A08G045) += r9a08g045s33-smarc.dtb dtb-$(CONFIG_ARCH_R9A09G011) += r9a09g011-v2mevk2.dtb +dtb-$(CONFIG_ARCH_R9A09G047) += r9a09g047e57-smarc.dtb + dtb-$(CONFIG_ARCH_R9A09G057) += r9a09g057h44-rzv2h-evk.dtb dtb-$(CONFIG_ARCH_RCAR_GEN3) += draak-ebisu-panel-aa104xd12.dtbo diff --git a/arch/arm64/boot/dts/renesas/r8a779a0-falcon-ethernet.dtsi b/arch/arm64/boot/dts/renesas/r8a779a0-falcon-ethernet.dtsi index e11bf9ace776..2a8537e13873 100644 --- a/arch/arm64/boot/dts/renesas/r8a779a0-falcon-ethernet.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779a0-falcon-ethernet.dtsi @@ -5,6 +5,121 @@ * Copyright (C) 2021 Glider bv */ +/ { + aliases { + ethernet1 = &avb1; + ethernet2 = &avb2; + ethernet3 = &avb3; + ethernet4 = &avb4; + ethernet5 = &avb5; + }; +}; + +&avb1 { + pinctrl-0 = <&avb1_pins>; + pinctrl-names = "default"; + phy-handle = <&avb1_phy>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + reset-gpios = <&gpio5 15 GPIO_ACTIVE_LOW>; + reset-post-delay-us = <4000>; + + avb1_phy: ethernet-phy@7 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <7>; + interrupts-extended = <&gpio5 16 IRQ_TYPE_LEVEL_LOW>; + }; + }; +}; + +&avb2 { + pinctrl-0 = <&avb2_pins>; + pinctrl-names = "default"; + phy-handle = <&avb2_phy>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + reset-gpios = <&gpio6 15 GPIO_ACTIVE_LOW>; + reset-post-delay-us = <4000>; + + avb2_phy: ethernet-phy@7 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <7>; + interrupts-extended = <&gpio6 16 IRQ_TYPE_LEVEL_LOW>; + }; + }; +}; + +&avb3 { + pinctrl-0 = <&avb3_pins>; + pinctrl-names = "default"; + phy-handle = <&avb3_phy>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + reset-gpios = <&gpio7 15 GPIO_ACTIVE_LOW>; + reset-post-delay-us = <4000>; + + avb3_phy: ethernet-phy@7 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <7>; + interrupts-extended = <&gpio7 16 IRQ_TYPE_LEVEL_LOW>; + }; + }; +}; + +&avb4 { + pinctrl-0 = <&avb4_pins>; + pinctrl-names = "default"; + phy-handle = <&avb4_phy>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + reset-gpios = <&gpio8 15 GPIO_ACTIVE_LOW>; + reset-post-delay-us = <4000>; + + avb4_phy: ethernet-phy@7 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <7>; + interrupts-extended = <&gpio8 16 IRQ_TYPE_LEVEL_LOW>; + }; + }; +}; + +&avb5 { + pinctrl-0 = <&avb5_pins>; + pinctrl-names = "default"; + phy-handle = <&avb5_phy>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + reset-gpios = <&gpio9 15 GPIO_ACTIVE_LOW>; + reset-post-delay-us = <4000>; + + avb5_phy: ethernet-phy@7 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <7>; + interrupts-extended = <&gpio9 16 IRQ_TYPE_LEVEL_LOW>; + }; + }; +}; + &i2c0 { eeprom@53 { compatible = "rohm,br24g01", "atmel,24c01"; @@ -13,3 +128,130 @@ pagesize = <8>; }; }; + +&pfc { + avb1_pins: avb1 { + mux { + groups = "avb1_link", "avb1_mdio", "avb1_rgmii", + "avb1_txcrefclk"; + function = "avb1"; + }; + + link { + groups = "avb1_link"; + bias-disable; + }; + + mdio { + groups = "avb1_mdio"; + drive-strength = <24>; + bias-disable; + }; + + rgmii { + groups = "avb1_rgmii"; + drive-strength = <24>; + bias-disable; + }; + }; + + avb2_pins: avb2 { + mux { + groups = "avb2_link", "avb2_mdio", "avb2_rgmii", + "avb2_txcrefclk"; + function = "avb2"; + }; + + link { + groups = "avb2_link"; + bias-disable; + }; + + mdio { + groups = "avb2_mdio"; + drive-strength = <24>; + bias-disable; + }; + + rgmii { + groups = "avb2_rgmii"; + drive-strength = <24>; + bias-disable; + }; + }; + + avb3_pins: avb3 { + mux { + groups = "avb3_link", "avb3_mdio", "avb3_rgmii", + "avb3_txcrefclk"; + function = "avb3"; + }; + + link { + groups = "avb3_link"; + bias-disable; + }; + + mdio { + groups = "avb3_mdio"; + drive-strength = <24>; + bias-disable; + }; + + rgmii { + groups = "avb3_rgmii"; + drive-strength = <24>; + bias-disable; + }; + }; + + avb4_pins: avb4 { + mux { + groups = "avb4_link", "avb4_mdio", "avb4_rgmii", + "avb4_txcrefclk"; + function = "avb4"; + }; + + link { + groups = "avb4_link"; + bias-disable; + }; + + mdio { + groups = "avb4_mdio"; + drive-strength = <24>; + bias-disable; + }; + + rgmii { + groups = "avb4_rgmii"; + drive-strength = <24>; + bias-disable; + }; + }; + + avb5_pins: avb5 { + mux { + groups = "avb5_link", "avb5_mdio", "avb5_rgmii", + "avb5_txcrefclk"; + function = "avb5"; + }; + + link { + groups = "avb5_link"; + bias-disable; + }; + + mdio { + groups = "avb5_mdio"; + drive-strength = <24>; + bias-disable; + }; + + rgmii { + groups = "avb5_rgmii"; + drive-strength = <24>; + bias-disable; + }; + }; +}; diff --git a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi index 7156b1a542e8..fe6d97859e4a 100644 --- a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi @@ -765,8 +765,6 @@ rx-internal-delay-ps = <0>; tx-internal-delay-ps = <0>; iommus = <&ipmmu_ds1 1>; - #address-cells = <1>; - #size-cells = <0>; status = "disabled"; }; @@ -814,8 +812,6 @@ rx-internal-delay-ps = <0>; tx-internal-delay-ps = <0>; iommus = <&ipmmu_ds1 2>; - #address-cells = <1>; - #size-cells = <0>; status = "disabled"; }; @@ -863,8 +859,6 @@ rx-internal-delay-ps = <0>; tx-internal-delay-ps = <0>; iommus = <&ipmmu_ds1 3>; - #address-cells = <1>; - #size-cells = <0>; status = "disabled"; }; @@ -912,8 +906,6 @@ rx-internal-delay-ps = <0>; tx-internal-delay-ps = <0>; iommus = <&ipmmu_ds1 4>; - #address-cells = <1>; - #size-cells = <0>; status = "disabled"; }; @@ -961,8 +953,6 @@ rx-internal-delay-ps = <0>; tx-internal-delay-ps = <0>; iommus = <&ipmmu_ds1 11>; - #address-cells = <1>; - #size-cells = <0>; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/renesas/r8a779g2-white-hawk-single.dts b/arch/arm64/boot/dts/renesas/r8a779g2-white-hawk-single.dts index 0062362b0ba0..48befde38937 100644 --- a/arch/arm64/boot/dts/renesas/r8a779g2-white-hawk-single.dts +++ b/arch/arm64/boot/dts/renesas/r8a779g2-white-hawk-single.dts @@ -7,70 +7,10 @@ /dts-v1/; #include "r8a779g2.dtsi" -#include "white-hawk-cpu-common.dtsi" -#include "white-hawk-common.dtsi" +#include "white-hawk-single.dtsi" / { model = "Renesas White Hawk Single board based on r8a779g2"; compatible = "renesas,white-hawk-single", "renesas,r8a779g2", "renesas,r8a779g0"; }; - -&hscif0 { - uart-has-rtscts; -}; - -&hscif0_pins { - groups = "hscif0_data", "hscif0_ctrl"; - function = "hscif0"; -}; - -&pfc { - tsn0_pins: tsn0 { - mux { - groups = "tsn0_link", "tsn0_mdio", "tsn0_rgmii", - "tsn0_txcrefclk"; - function = "tsn0"; - }; - - link { - groups = "tsn0_link"; - bias-disable; - }; - - mdio { - groups = "tsn0_mdio"; - drive-strength = <24>; - bias-disable; - }; - - rgmii { - groups = "tsn0_rgmii"; - drive-strength = <24>; - bias-disable; - }; - }; -}; - -&tsn0 { - pinctrl-0 = <&tsn0_pins>; - pinctrl-names = "default"; - phy-mode = "rgmii"; - phy-handle = <&phy3>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - reset-gpios = <&gpio1 23 GPIO_ACTIVE_LOW>; - reset-post-delay-us = <4000>; - - phy3: ethernet-phy@0 { - compatible = "ethernet-phy-id002b.0980", - "ethernet-phy-ieee802.3-c22"; - reg = <0>; - interrupts-extended = <&gpio4 3 IRQ_TYPE_LEVEL_LOW>; - }; - }; -}; diff --git a/arch/arm64/boot/dts/renesas/r8a779g3-white-hawk-single.dts b/arch/arm64/boot/dts/renesas/r8a779g3-white-hawk-single.dts new file mode 100644 index 000000000000..cd466d858854 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r8a779g3-white-hawk-single.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the R-Car V4H ES3.0 White Hawk Single board + * + * Copyright (C) 2024 Glider bv + */ + +/dts-v1/; +#include "r8a779g3.dtsi" +#include "white-hawk-single.dtsi" + +/ { + model = "Renesas White Hawk Single board based on r8a779g3"; + compatible = "renesas,white-hawk-single", "renesas,r8a779g3", + "renesas,r8a779g0"; +}; diff --git a/arch/arm64/boot/dts/renesas/r8a779g3.dtsi b/arch/arm64/boot/dts/renesas/r8a779g3.dtsi new file mode 100644 index 000000000000..0295858a0260 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r8a779g3.dtsi @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the R-Car V4H (R8A779G3) SoC + * + * Copyright (C) 2024 Glider bv + */ + +#include "r8a779g0.dtsi" + +/ { + compatible = "renesas,r8a779g3", "renesas,r8a779g0"; +}; diff --git a/arch/arm64/boot/dts/renesas/r8a779h0-gray-hawk-single.dts b/arch/arm64/boot/dts/renesas/r8a779h0-gray-hawk-single.dts index 58eabcc7e0e0..18fd52f55de5 100644 --- a/arch/arm64/boot/dts/renesas/r8a779h0-gray-hawk-single.dts +++ b/arch/arm64/boot/dts/renesas/r8a779h0-gray-hawk-single.dts @@ -30,6 +30,7 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/input.h> #include <dt-bindings/leds/common.h> +#include <dt-bindings/media/video-interfaces.h> #include "r8a779h0.dtsi" @@ -59,6 +60,12 @@ stdout-path = "serial0:921600n8"; }; + sn65dsi86_refclk: clk-x6 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <38400000>; + }; + keys { compatible = "gpio-keys"; @@ -132,22 +139,43 @@ #clock-cells = <0>; }; + mini-dp-con { + compatible = "dp-connector"; + label = "CN5"; + type = "mini"; + + port { + mini_dp_con_in: endpoint { + remote-endpoint = <&sn65dsi86_out0>; + }; + }; + }; + + reg_1p2v: regulator-1p2v { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.2V"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-boot-on; + regulator-always-on; + }; + reg_1p8v: regulator-1p8v { - compatible = "regulator-fixed"; - regulator-name = "fixed-1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; + compatible = "regulator-fixed"; + regulator-name = "fixed-1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; }; reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "fixed-3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; }; sound_mux: sound-mux { @@ -205,6 +233,65 @@ }; }; +&dsi0 { + status = "okay"; + + ports { + port@1 { + reg = <1>; + + dsi0_out: endpoint { + remote-endpoint = <&sn65dsi86_in0>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + +&du { + status = "okay"; +}; + +&csi40 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + csi40_in: endpoint { + bus-type = <MEDIA_BUS_TYPE_CSI2_DPHY>; + clock-lanes = <0>; + data-lanes = <1 2 3 4>; + remote-endpoint = <&max96724_out0>; + }; + }; + }; +}; + +&csi41 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + csi41_in: endpoint { + bus-type = <MEDIA_BUS_TYPE_CSI2_DPHY>; + clock-lanes = <0>; + data-lanes = <1 2 3 4>; + remote-endpoint = <&max96724_out1>; + }; + }; + }; +}; + &extal_clk { clock-frequency = <16666666>; }; @@ -255,6 +342,20 @@ #interrupt-cells = <2>; }; + io_expander_b: gpio@21 { + compatible = "onnn,pca9654"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + }; + + io_expander_c: gpio@22 { + compatible = "onnn,pca9654"; + reg = <0x22>; + gpio-controller; + #gpio-cells = <2>; + }; + eeprom@50 { compatible = "rohm,br24g01", "atmel,24c01"; label = "cpu-board"; @@ -284,6 +385,97 @@ }; }; +&i2c1 { + pinctrl-0 = <&i2c1_pins>; + pinctrl-names = "default"; + + status = "okay"; + clock-frequency = <400000>; + + bridge@2c { + pinctrl-0 = <&irq0_pins>; + pinctrl-names = "default"; + + compatible = "ti,sn65dsi86"; + reg = <0x2c>; + + clocks = <&sn65dsi86_refclk>; + clock-names = "refclk"; + + interrupts-extended = <&intc_ex 0 IRQ_TYPE_LEVEL_HIGH>; + + enable-gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; + + vccio-supply = <®_1p8v>; + vpll-supply = <®_1p8v>; + vcca-supply = <®_1p2v>; + vcc-supply = <®_1p2v>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + sn65dsi86_in0: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + + port@1 { + reg = <1>; + + sn65dsi86_out0: endpoint { + remote-endpoint = <&mini_dp_con_in>; + }; + }; + }; + }; + + gmsl0: gmsl-deserializer@4e { + compatible = "maxim,max96724"; + reg = <0x4e>; + enable-gpios = <&io_expander_b 0 GPIO_ACTIVE_HIGH>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@4 { + reg = <4>; + max96724_out0: endpoint { + bus-type = <MEDIA_BUS_TYPE_CSI2_DPHY>; + clock-lanes = <0>; + data-lanes = <1 2 3 4>; + remote-endpoint = <&csi40_in>; + }; + }; + }; + }; + + gmsl1: gmsl-deserializer@4f { + compatible = "maxim,max96724"; + reg = <0x4f>; + enable-gpios = <&io_expander_c 0 GPIO_ACTIVE_HIGH>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@4 { + reg = <4>; + max96724_out1: endpoint { + bus-type = <MEDIA_BUS_TYPE_CSI2_DPHY>; + clock-lanes = <0>; + data-lanes = <1 2 3 4>; + remote-endpoint = <&csi41_in>; + }; + }; + }; + }; +}; + &i2c3 { pinctrl-0 = <&i2c3_pins>; pinctrl-names = "default"; @@ -307,6 +499,14 @@ }; }; +&isp0 { + status = "okay"; +}; + +&isp1 { + status = "okay"; +}; + &mmc0 { pinctrl-0 = <&mmc_pins>; pinctrl-1 = <&mmc_pins>; @@ -388,11 +588,21 @@ function = "i2c0"; }; + i2c1_pins: i2c1 { + groups = "i2c1"; + function = "i2c1"; + }; + i2c3_pins: i2c3 { groups = "i2c3"; function = "i2c3"; }; + irq0_pins: irq0_pins { + groups = "intc_ex_irq0_a"; + function = "intc_ex"; + }; + keys_pins: keys { pins = "GP_5_0", "GP_5_1", "GP_5_2"; bias-pull-up; @@ -494,3 +704,67 @@ &scif_clk2 { clock-frequency = <24000000>; }; + +&vin00 { + status = "okay"; +}; + +&vin01 { + status = "okay"; +}; + +&vin02 { + status = "okay"; +}; + +&vin03 { + status = "okay"; +}; + +&vin04 { + status = "okay"; +}; + +&vin05 { + status = "okay"; +}; + +&vin06 { + status = "okay"; +}; + +&vin07 { + status = "okay"; +}; + +&vin08 { + status = "okay"; +}; + +&vin09 { + status = "okay"; +}; + +&vin10 { + status = "okay"; +}; + +&vin11 { + status = "okay"; +}; + +&vin12 { + status = "okay"; +}; + +&vin13 { + status = "okay"; +}; + +&vin14 { + status = "okay"; +}; + +&vin15 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/renesas/r8a779h0.dtsi b/arch/arm64/boot/dts/renesas/r8a779h0.dtsi index facfff4b9cdc..d0c01c0fdda2 100644 --- a/arch/arm64/boot/dts/renesas/r8a779h0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779h0.dtsi @@ -1900,6 +1900,50 @@ }; }; + fcpvd0: fcp@fea10000 { + compatible = "renesas,fcpv"; + reg = <0 0xfea10000 0 0x200>; + clocks = <&cpg CPG_MOD 508>; + power-domains = <&sysc R8A779H0_PD_C4>; + resets = <&cpg 508>; + }; + + vspd0: vsp@fea20000 { + compatible = "renesas,vsp2"; + reg = <0 0xfea20000 0 0x8000>; + interrupts = <GIC_SPI 546 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 830>; + power-domains = <&sysc R8A779H0_PD_C4>; + resets = <&cpg 830>; + renesas,fcp = <&fcpvd0>; + }; + + du: display@feb00000 { + compatible = "renesas,du-r8a779h0"; + reg = <0 0xfeb00000 0 0x40000>; + interrupts = <GIC_SPI 523 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 411>; + clock-names = "du.0"; + power-domains = <&sysc R8A779H0_PD_C4>; + resets = <&cpg 411>; + reset-names = "du.0"; + renesas,vsps = <&vspd0 0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + du_out_dsi0: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; + }; + }; + isp0: isp@fed00000 { compatible = "renesas,r8a779h0-isp", "renesas,rcar-gen4-isp"; @@ -2068,6 +2112,35 @@ }; }; + dsi0: dsi-encoder@fed80000 { + compatible = "renesas,r8a779h0-dsi-csi2-tx"; + reg = <0 0xfed80000 0 0x10000>; + clocks = <&cpg CPG_MOD 415>, + <&cpg CPG_CORE R8A779H0_CLK_DSIEXT>, + <&cpg CPG_CORE R8A779H0_CLK_DSIREF>; + clock-names = "fck", "dsi", "pll"; + power-domains = <&sysc R8A779H0_PD_C4>; + resets = <&cpg 415>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi0_in: endpoint { + remote-endpoint = <&du_out_dsi0>; + }; + }; + + port@1 { + reg = <1>; + }; + }; + }; + prr: chipid@fff00044 { compatible = "renesas,prr"; reg = <0 0xfff00044 0 4>; diff --git a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi index be8a0a768c65..a9b98db9ef95 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi @@ -14,6 +14,20 @@ #address-cells = <2>; #size-cells = <2>; + audio_clk1: audio1-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by boards that provide it. */ + clock-frequency = <0>; + }; + + audio_clk2: audio2-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by boards that provide it. */ + clock-frequency = <0>; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -73,6 +87,96 @@ status = "disabled"; }; + scif1: serial@1004bc00 { + compatible = "renesas,scif-r9a08g045", "renesas,scif-r9a07g044"; + reg = <0 0x1004bc00 0 0x400>; + interrupts = <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "eri", "rxi", "txi", + "bri", "dri", "tei"; + clocks = <&cpg CPG_MOD R9A08G045_SCIF1_CLK_PCK>; + clock-names = "fck"; + power-domains = <&cpg>; + resets = <&cpg R9A08G045_SCIF1_RST_SYSTEM_N>; + status = "disabled"; + }; + + scif2: serial@1004c000 { + compatible = "renesas,scif-r9a08g045", "renesas,scif-r9a07g044"; + reg = <0 0x1004c000 0 0x400>; + interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "eri", "rxi", "txi", + "bri", "dri", "tei"; + clocks = <&cpg CPG_MOD R9A08G045_SCIF2_CLK_PCK>; + clock-names = "fck"; + power-domains = <&cpg>; + resets = <&cpg R9A08G045_SCIF2_RST_SYSTEM_N>; + status = "disabled"; + }; + + scif3: serial@1004c400 { + compatible = "renesas,scif-r9a08g045", "renesas,scif-r9a07g044"; + reg = <0 0x1004c400 0 0x400>; + interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "eri", "rxi", "txi", + "bri", "dri", "tei"; + clocks = <&cpg CPG_MOD R9A08G045_SCIF3_CLK_PCK>; + clock-names = "fck"; + power-domains = <&cpg>; + resets = <&cpg R9A08G045_SCIF3_RST_SYSTEM_N>; + status = "disabled"; + }; + + scif4: serial@1004c800 { + compatible = "renesas,scif-r9a08g045", "renesas,scif-r9a07g044"; + reg = <0 0x1004c800 0 0x400>; + interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "eri", "rxi", "txi", + "bri", "dri", "tei"; + clocks = <&cpg CPG_MOD R9A08G045_SCIF4_CLK_PCK>; + clock-names = "fck"; + power-domains = <&cpg>; + resets = <&cpg R9A08G045_SCIF4_RST_SYSTEM_N>; + status = "disabled"; + }; + + scif5: serial@1004e000 { + compatible = "renesas,scif-r9a08g045", "renesas,scif-r9a07g044"; + reg = <0 0x1004e000 0 0x400>; + interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "eri", "rxi", "txi", + "bri", "dri", "tei"; + clocks = <&cpg CPG_MOD R9A08G045_SCIF5_CLK_PCK>; + clock-names = "fck"; + power-domains = <&cpg>; + resets = <&cpg R9A08G045_SCIF5_RST_SYSTEM_N>; + status = "disabled"; + }; + rtc: rtc@1004ec00 { compatible = "renesas,r9a08g045-rtca3", "renesas,rz-rtca3"; reg = <0 0x1004ec00 0 0x400>; @@ -87,6 +191,59 @@ status = "disabled"; }; + adc: adc@10058000 { + compatible = "renesas,r9a08g045-adc"; + reg = <0 0x10058000 0 0x1000>; + interrupts = <GIC_SPI 312 IRQ_TYPE_EDGE_RISING>; + clocks = <&cpg CPG_MOD R9A08G045_ADC_ADCLK>, + <&cpg CPG_MOD R9A08G045_ADC_PCLK>; + clock-names = "adclk", "pclk"; + resets = <&cpg R9A08G045_ADC_PRESETN>, + <&cpg R9A08G045_ADC_ADRST_N>; + reset-names = "presetn", "adrst-n"; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + #io-channel-cells = <1>; + status = "disabled"; + + channel@0 { + reg = <0>; + }; + + channel@1 { + reg = <1>; + }; + + channel@2 { + reg = <2>; + }; + + channel@3 { + reg = <3>; + }; + + channel@4 { + reg = <4>; + }; + + channel@5 { + reg = <5>; + }; + + channel@6 { + reg = <6>; + }; + + channel@7 { + reg = <7>; + }; + + channel@8 { + reg = <8>; + }; + }; + vbattb: clock-controller@1005c000 { compatible = "renesas,r9a08g045-vbattb"; reg = <0 0x1005c000 0 0x1000>; @@ -187,6 +344,86 @@ status = "disabled"; }; + ssi0: ssi@100a8000 { + compatible = "renesas,r9a08g045-ssi", + "renesas,rz-ssi"; + reg = <0 0x100a8000 0 0x400>; + interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 241 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 242 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "int_req", "dma_rx", "dma_tx"; + clocks = <&cpg CPG_MOD R9A08G045_SSI0_PCLK2>, + <&cpg CPG_MOD R9A08G045_SSI0_PCLK_SFR>, + <&audio_clk1>, <&audio_clk2>; + clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2"; + resets = <&cpg R9A08G045_SSI0_RST_M2_REG>; + dmas = <&dmac 0x2665>, <&dmac 0x2666>; + dma-names = "tx", "rx"; + power-domains = <&cpg>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + ssi1: ssi@100a8400 { + compatible = "renesas,r9a08g045-ssi", + "renesas,rz-ssi"; + reg = <0 0x100a8400 0 0x400>; + interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 244 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 245 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "int_req", "dma_rx", "dma_tx"; + clocks = <&cpg CPG_MOD R9A08G045_SSI1_PCLK2>, + <&cpg CPG_MOD R9A08G045_SSI1_PCLK_SFR>, + <&audio_clk1>, <&audio_clk2>; + clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2"; + resets = <&cpg R9A08G045_SSI1_RST_M2_REG>; + dmas = <&dmac 0x2669>, <&dmac 0x266a>; + dma-names = "tx", "rx"; + power-domains = <&cpg>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + ssi2: ssi@100a8800 { + compatible = "renesas,r9a08g045-ssi", + "renesas,rz-ssi"; + reg = <0 0x100a8800 0 0x400>; + interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 247 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 248 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "int_req", "dma_rx", "dma_tx"; + clocks = <&cpg CPG_MOD R9A08G045_SSI2_PCLK2>, + <&cpg CPG_MOD R9A08G045_SSI2_PCLK_SFR>, + <&audio_clk1>, <&audio_clk2>; + clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2"; + resets = <&cpg R9A08G045_SSI2_RST_M2_REG>; + dmas = <&dmac 0x266d>, <&dmac 0x266e>; + dma-names = "tx", "rx"; + power-domains = <&cpg>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + ssi3: ssi@100a8c00 { + compatible = "renesas,r9a08g045-ssi", + "renesas,rz-ssi"; + reg = <0 0x100a8c00 0 0x400>; + interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 250 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 251 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "int_req", "dma_rx", "dma_tx"; + clocks = <&cpg CPG_MOD R9A08G045_SSI3_PCLK2>, + <&cpg CPG_MOD R9A08G045_SSI3_PCLK_SFR>, + <&audio_clk1>, <&audio_clk2>; + clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2"; + resets = <&cpg R9A08G045_SSI3_RST_M2_REG>; + dmas = <&dmac 0x2671>, <&dmac 0x2672>; + dma-names = "tx", "rx"; + power-domains = <&cpg>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + cpg: clock-controller@11010000 { compatible = "renesas,r9a08g045-cpg"; reg = <0 0x11010000 0 0x10000>; diff --git a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi new file mode 100644 index 000000000000..7a422e9ad29e --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi @@ -0,0 +1,374 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/G3E SoC + * + * Copyright (C) 2024 Renesas Electronics Corp. + */ + +#include <dt-bindings/clock/renesas,r9a09g047-cpg.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/ { + compatible = "renesas,r9a09g047"; + #address-cells = <2>; + #size-cells = <2>; + + audio_extal_clk: audio-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + + /* + * The default cluster table is based on the assumption that the PLLCA55 clock + * frequency is set to 1.7GHz. The PLLCA55 clock frequency can be set to + * 1.7/1.6/1.5/1.1 GHz based on the BOOTPLLCA_0/1 pins (and additionally can be + * clocked to 1.8GHz as well). The table below should be overridden in the board + * DTS based on the PLLCA55 clock frequency. + */ + cluster0_opp: opp-table-0 { + compatible = "operating-points-v2"; + + opp-1700000000 { + opp-hz = /bits/ 64 <1700000000>; + opp-microvolt = <900000>; + clock-latency-ns = <300000>; + }; + opp-850000000 { + opp-hz = /bits/ 64 <850000000>; + opp-microvolt = <800000>; + clock-latency-ns = <300000>; + }; + opp-425000000 { + opp-hz = /bits/ 64 <425000000>; + opp-microvolt = <800000>; + clock-latency-ns = <300000>; + }; + opp-212500000 { + opp-hz = /bits/ 64 <212500000>; + opp-microvolt = <800000>; + clock-latency-ns = <300000>; + opp-suspend; + }; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,cortex-a55"; + reg = <0>; + device_type = "cpu"; + next-level-cache = <&L3_CA55>; + enable-method = "psci"; + clocks = <&cpg CPG_CORE R9A09G047_CA55_0_CORECLK0>; + operating-points-v2 = <&cluster0_opp>; + }; + + cpu1: cpu@100 { + compatible = "arm,cortex-a55"; + reg = <0x100>; + device_type = "cpu"; + next-level-cache = <&L3_CA55>; + enable-method = "psci"; + clocks = <&cpg CPG_CORE R9A09G047_CA55_0_CORECLK1>; + operating-points-v2 = <&cluster0_opp>; + }; + + cpu2: cpu@200 { + compatible = "arm,cortex-a55"; + reg = <0x200>; + device_type = "cpu"; + next-level-cache = <&L3_CA55>; + enable-method = "psci"; + clocks = <&cpg CPG_CORE R9A09G047_CA55_0_CORECLK2>; + operating-points-v2 = <&cluster0_opp>; + }; + + cpu3: cpu@300 { + compatible = "arm,cortex-a55"; + reg = <0x300>; + device_type = "cpu"; + next-level-cache = <&L3_CA55>; + enable-method = "psci"; + clocks = <&cpg CPG_CORE R9A09G047_CA55_0_CORECLK3>; + operating-points-v2 = <&cluster0_opp>; + }; + + L3_CA55: cache-controller-0 { + compatible = "cache"; + cache-unified; + cache-size = <0x100000>; + cache-level = <3>; + }; + }; + + psci { + compatible = "arm,psci-1.0", "arm,psci-0.2"; + method = "smc"; + }; + + qextal_clk: qextal-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + + rtxin_clk: rtxin-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + + soc: soc { + compatible = "simple-bus"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + cpg: clock-controller@10420000 { + compatible = "renesas,r9a09g047-cpg"; + reg = <0 0x10420000 0 0x10000>; + clocks = <&audio_extal_clk>, <&rtxin_clk>, <&qextal_clk>; + clock-names = "audio_extal", "rtxin", "qextal"; + #clock-cells = <2>; + #reset-cells = <1>; + #power-domain-cells = <0>; + }; + + scif0: serial@11c01400 { + compatible = "renesas,scif-r9a09g047", "renesas,scif-r9a09g057"; + reg = <0 0x11c01400 0 0x400>; + interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 534 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 536 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 537 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "eri", "rxi", "txi", "bri", "dri", + "tei", "tei-dri", "rxi-edge", "txi-edge"; + clocks = <&cpg CPG_MOD 0x8f>; + clock-names = "fck"; + power-domains = <&cpg>; + resets = <&cpg 0x95>; + status = "disabled"; + }; + + i2c0: i2c@14400400 { + compatible = "renesas,riic-r9a09g047", "renesas,riic-r9a09g057"; + reg = <0 0x14400400 0 0x400>; + interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 507 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 506 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tei", "ri", "ti", "spi", "sti", + "naki", "ali", "tmoi"; + clocks = <&cpg CPG_MOD 0x94>; + resets = <&cpg 0x98>; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@14400800 { + compatible = "renesas,riic-r9a09g047", "renesas,riic-r9a09g057"; + reg = <0 0x14400800 0 0x400>; + interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 509 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 508 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tei", "ri", "ti", "spi", "sti", + "naki", "ali", "tmoi"; + clocks = <&cpg CPG_MOD 0x95>; + resets = <&cpg 0x99>; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@14400c00 { + compatible = "renesas,riic-r9a09g047", "renesas,riic-r9a09g057"; + reg = <0 0x14400c00 0 0x400>; + interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 511 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 510 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tei", "ri", "ti", "spi", "sti", + "naki", "ali", "tmoi"; + clocks = <&cpg CPG_MOD 0x96>; + resets = <&cpg 0x9a>; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c@14401000 { + compatible = "renesas,riic-r9a09g047", "renesas,riic-r9a09g057"; + reg = <0 0x14401000 0 0x400>; + interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 513 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 512 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tei", "ri", "ti", "spi", "sti", + "naki", "ali", "tmoi"; + clocks = <&cpg CPG_MOD 0x97>; + resets = <&cpg 0x9b>; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c4: i2c@14401400 { + compatible = "renesas,riic-r9a09g047", "renesas,riic-r9a09g057"; + reg = <0 0x14401400 0 0x400>; + interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 515 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 514 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tei", "ri", "ti", "spi", "sti", + "naki", "ali", "tmoi"; + clocks = <&cpg CPG_MOD 0x98>; + resets = <&cpg 0x9c>; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c5: i2c@14401800 { + compatible = "renesas,riic-r9a09g047", "renesas,riic-r9a09g057"; + reg = <0 0x14401800 0 0x400>; + interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 517 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 516 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tei", "ri", "ti", "spi", "sti", + "naki", "ali", "tmoi"; + clocks = <&cpg CPG_MOD 0x99>; + resets = <&cpg 0x9d>; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c6: i2c@14401c00 { + compatible = "renesas,riic-r9a09g047", "renesas,riic-r9a09g057"; + reg = <0 0x14401c00 0 0x400>; + interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 519 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 518 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tei", "ri", "ti", "spi", "sti", + "naki", "ali", "tmoi"; + clocks = <&cpg CPG_MOD 0x9a>; + resets = <&cpg 0x9e>; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c7: i2c@14402000 { + compatible = "renesas,riic-r9a09g047", "renesas,riic-r9a09g057"; + reg = <0 0x14402000 0 0x400>; + interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 521 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 520 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tei", "ri", "ti", "spi", "sti", + "naki", "ali", "tmoi"; + clocks = <&cpg CPG_MOD 0x9b>; + resets = <&cpg 0x9f>; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c8: i2c@11c01000 { + compatible = "renesas,riic-r9a09g047", "renesas,riic-r9a09g057"; + reg = <0 0x11c01000 0 0x400>; + interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 523 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 522 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tei", "ri", "ti", "spi", "sti", + "naki", "ali", "tmoi"; + clocks = <&cpg CPG_MOD 0x93>; + resets = <&cpg 0xa0>; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + gic: interrupt-controller@14900000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x14900000 0 0x20000>, + <0x0 0x14940000 0 0x80000>; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, + <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, + <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, + <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>, + <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt"; + }; +}; diff --git a/arch/arm64/boot/dts/renesas/r9a09g047e37.dtsi b/arch/arm64/boot/dts/renesas/r9a09g047e37.dtsi new file mode 100644 index 000000000000..e50d9159e832 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r9a09g047e37.dtsi @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/G3E R9A09G047E37 SoC specific parts + * + * Copyright (C) 2024 Renesas Electronics Corp. + */ + +/dts-v1/; +#include "r9a09g047.dtsi" + +/ { + compatible = "renesas,r9a09g047e37", "renesas,r9a09g047"; + + cpus { + /delete-node/ cpu@200; + /delete-node/ cpu@300; + }; +}; diff --git a/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts b/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts new file mode 100644 index 000000000000..d4d61bd03969 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/G3E SMARC EVK board + * + * Copyright (C) 2024 Renesas Electronics Corp. + */ + +/dts-v1/; + +#include "r9a09g047e57.dtsi" +#include "rzg3e-smarc-som.dtsi" +#include "renesas-smarc2.dtsi" + +/ { + model = "Renesas SMARC EVK version 2 based on r9a09g047e57"; + compatible = "renesas,smarc2-evk", "renesas,rzg3e-smarcm", + "renesas,r9a09g047e57", "renesas,r9a09g047"; +}; diff --git a/arch/arm64/boot/dts/renesas/r9a09g047e57.dtsi b/arch/arm64/boot/dts/renesas/r9a09g047e57.dtsi new file mode 100644 index 000000000000..98a5faebd47a --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r9a09g047e57.dtsi @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/G3E R9A09G047E57 SoC specific parts + * + * Copyright (C) 2024 Renesas Electronics Corp. + */ + +/dts-v1/; +#include "r9a09g047.dtsi" + +/ { + compatible = "renesas,r9a09g047e57", "renesas,r9a09g047"; +}; diff --git a/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi b/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi new file mode 100644 index 000000000000..e378d55e6e9b --- /dev/null +++ b/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ SMARC Carrier-II Board. + * + * Copyright (C) 2024 Renesas Electronics Corp. + */ + +/ { + model = "Renesas RZ SMARC Carrier-II Board"; + compatible = "renesas,smarc2-evk"; + + chosen { + bootargs = "ignore_loglevel"; + stdout-path = "serial3:115200n8"; + }; + + aliases { + serial3 = &scif0; + }; +}; + +&scif0 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi new file mode 100644 index 000000000000..6b583ae2ac52 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the R9A09G047E57 SMARC SoM board. + * + * Copyright (C) 2024 Renesas Electronics Corp. + */ + +/ { + compatible = "renesas,rzg3e-smarcm", "renesas,r9a09g047e57", "renesas,r9a09g047"; + + memory@48000000 { + device_type = "memory"; + /* First 128MB is reserved for secure area. */ + reg = <0x0 0x48000000 0x0 0xf8000000>; + }; +}; + +&audio_extal_clk { + clock-frequency = <48000000>; +}; + +&qextal_clk { + clock-frequency = <24000000>; +}; + +&rtxin_clk { + clock-frequency = <32768>; +}; diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi index 2ed01d391554..ef12c1c462a7 100644 --- a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi @@ -43,11 +43,6 @@ #endif }; - chosen { - bootargs = "ignore_loglevel"; - stdout-path = "serial0:115200n8"; - }; - memory@48000000 { device_type = "memory"; /* First 128MB is reserved for secure area. */ @@ -63,7 +58,6 @@ enable-active-high; }; -#if SW_CONFIG2 == SW_ON vccq_sdhi0: regulator1 { compatible = "regulator-gpio"; regulator-name = "SDHI0 VccQ"; @@ -73,8 +67,8 @@ gpios-states = <1>; states = <3300000 1>, <1800000 0>; }; -#else - reg_1p8v: regulator1 { + + reg_1p8v: regulator2 { compatible = "regulator-fixed"; regulator-name = "fixed-1.8V"; regulator-min-microvolt = <1800000>; @@ -82,9 +76,17 @@ regulator-boot-on; regulator-always-on; }; -#endif - vcc_sdhi2: regulator2 { + reg_3p3v: regulator3 { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + vcc_sdhi2: regulator4 { compatible = "regulator-fixed"; regulator-name = "SDHI2 Vcc"; regulator-min-microvolt = <3300000>; @@ -92,6 +94,16 @@ gpios = <&pinctrl RZG2L_GPIO(8, 1) GPIO_ACTIVE_HIGH>; enable-active-high; }; + + x3_clk: x3-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; +}; + +&adc { + status = "okay"; }; #if SW_CONFIG3 == SW_ON @@ -152,6 +164,30 @@ &i2c1 { status = "okay"; + + versa3: clock-generator@68 { + compatible = "renesas,5l35023"; + reg = <0x68>; + clocks = <&x3_clk>; + #clock-cells = <1>; + assigned-clocks = <&versa3 0>, + <&versa3 1>, + <&versa3 2>, + <&versa3 3>, + <&versa3 4>, + <&versa3 5>; + assigned-clock-rates = <24000000>, + <12288000>, + <11289600>, + <25000000>, + <100000000>, + <100000000>; + renesas,settings = [ + 80 00 11 19 4c 42 dc 2f 06 7d 20 1a 5f 1e f2 27 + 00 40 00 00 00 00 00 00 06 0c 19 02 3f f0 90 86 + a0 80 30 30 9c + ]; + }; }; #if SW_CONFIG2 == SW_ON diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi index 4509151344c4..81b4ffd1417d 100644 --- a/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi @@ -12,10 +12,15 @@ / { aliases { i2c0 = &i2c0; - serial0 = &scif0; + serial3 = &scif0; mmc1 = &sdhi1; }; + chosen { + bootargs = "ignore_loglevel"; + stdout-path = "serial3:115200n8"; + }; + keys { compatible = "gpio-keys"; @@ -44,6 +49,23 @@ }; }; + snd_rzg3s: sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&cpu_dai>; + simple-audio-card,frame-master = <&cpu_dai>; + simple-audio-card,mclk-fs = <256>; + + cpu_dai: simple-audio-card,cpu { + sound-dai = <&ssi3>; + }; + + codec_dai: simple-audio-card,codec { + sound-dai = <&da7212>; + clocks = <&versa3 1>; + }; + }; + vcc_sdhi1: regulator-vcc-sdhi1 { compatible = "regulator-fixed"; regulator-name = "SDHI1 Vcc"; @@ -64,13 +86,56 @@ }; }; +&audio_clk2 { + clock-frequency = <12288000>; +}; + &i2c0 { status = "okay"; clock-frequency = <1000000>; + + da7212: codec@1a { + compatible = "dlg,da7212"; + reg = <0x1a>; + + clocks = <&versa3 1>; + clock-names = "mclk"; + + #sound-dai-cells = <0>; + + dlg,micbias1-lvl = <2500>; + dlg,micbias2-lvl = <2500>; + dlg,dmic-data-sel = "lrise_rfall"; + dlg,dmic-samplephase = "between_clkedge"; + dlg,dmic-clkrate = <3000000>; + + VDDA-supply = <®_1p8v>; + VDDSP-supply = <®_3p3v>; + VDDMIC-supply = <®_3p3v>; + VDDIO-supply = <®_1p8v>; + }; +}; + +&i2c1 { + status = "okay"; + + clock-frequency = <400000>; + + power-monitor@44 { + compatible = "renesas,isl28022"; + reg = <0x44>; + shunt-resistor-micro-ohms = <8000>; + renesas,average-samples = <32>; + }; }; &pinctrl { + audio_clock_pins: audio-clock { + pins = "AUDIO_CLK1", "AUDIO_CLK2"; + input-enable; + }; + key-1-gpio-hog { gpio-hog; gpios = <RZG2L_GPIO(18, 0) GPIO_ACTIVE_LOW>; @@ -128,6 +193,13 @@ pinmux = <RZG2L_PORT_PINMUX(0, 2, 1)>; /* SD1_CD */ }; }; + + ssi3_pins: ssi3 { + pinmux = <RZG2L_PORT_PINMUX(18, 2, 8)>, /* BCK */ + <RZG2L_PORT_PINMUX(18, 3, 8)>, /* RCK */ + <RZG2L_PORT_PINMUX(18, 4, 8)>, /* TXD */ + <RZG2L_PORT_PINMUX(18, 5, 8)>; /* RXD */ + }; }; &scif0 { @@ -148,3 +220,12 @@ max-frequency = <125000000>; status = "okay"; }; + +&ssi3 { + clocks = <&cpg CPG_MOD R9A08G045_SSI3_PCLK2>, + <&cpg CPG_MOD R9A08G045_SSI3_PCLK_SFR>, + <&versa3 2>, <&audio_clk2>; + pinctrl-names = "default"; + pinctrl-0 = <&ssi3_pins>, <&audio_clock_pins>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi b/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi index 5c211ed83049..2a157d1efb3d 100644 --- a/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi +++ b/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi @@ -4,8 +4,24 @@ * * Copyright (C) 2017 Renesas Electronics Corp. * Copyright (C) 2017 Cogent Embedded, Inc. + * + * Sample Audio settings: + * + * > amixer set "DVC Out" 1% + * > amixer set "DVC In" 20% + * + * // if you use xxxx-mix+split.dtsi + * > amixer -D hw:1 set "pcm3168a DAC1" 50% + * > amixer -D hw:1 set "pcm3168a DAC2" 50% + * > amixer -D hw:1 set "pcm3168a DAC3" 50% + * > amixer -D hw:1 set "pcm3168a DAC4" 50% + * + * // else + * > amixer -D hw:1 set "DAC1" 50% + * > amixer -D hw:1 set "DAC2" 50% + * > amixer -D hw:1 set "DAC3" 50% + * > amixer -D hw:1 set "DAC4" 50% */ - / { aliases { serial1 = &hscif0; diff --git a/arch/arm64/boot/dts/renesas/ulcb.dtsi b/arch/arm64/boot/dts/renesas/ulcb.dtsi index cb11abba7bef..0c58d816c375 100644 --- a/arch/arm64/boot/dts/renesas/ulcb.dtsi +++ b/arch/arm64/boot/dts/renesas/ulcb.dtsi @@ -4,6 +4,11 @@ * * Copyright (C) 2016 Renesas Electronics Corp. * Copyright (C) 2016 Cogent Embedded, Inc. + * + * Sample Audio settings: + * + * > amixer set "DVC Out" 1% + * > amixer set "DVC In" 20% */ #include <dt-bindings/gpio/gpio.h> diff --git a/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-ard-audio-da7212.dtso b/arch/arm64/boot/dts/renesas/white-hawk-ard-audio-da7212.dtso index e6cf304c77ee..c27b9b3d4e5f 100644 --- a/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-ard-audio-da7212.dtso +++ b/arch/arm64/boot/dts/renesas/white-hawk-ard-audio-da7212.dtso @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Device Tree Source for the White Hawk board with ARD-AUDIO-DA7212 Board + * Device Tree Source for White Hawk (Single) board with ARD-AUDIO-DA7212 board * * You can find and buy "ARD-AUDIO-DA7212" at Digi-Key * @@ -27,12 +27,12 @@ * +----------------------------+ * |Breakout board | * | | +---------------+ - * |CN34 (I2C CN) | |J1 | + * |CN(30)34 (I2C CN) | |J1 | * | I2C0_SCL pin3 |<----->| pin20 SCL | * | I2C0_SDA pin5 |<----->| pin18 SDA | * | | +---------------+ * | | +-----------------------+ - * |CN4 (Power) | |J7 | + * |CN(300)4 (Power) | |J7 | * | 3v3 (v) pin9 |<----->| pin4 / pin8 3.3v | * | GND (v) pin3 / pin4 |<----->| pin12 / pin14 GND | * +----------------------------+ +-----------------------+ diff --git a/arch/arm64/boot/dts/renesas/white-hawk-single.dtsi b/arch/arm64/boot/dts/renesas/white-hawk-single.dtsi new file mode 100644 index 000000000000..20e8232f2f32 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/white-hawk-single.dtsi @@ -0,0 +1,73 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the White Hawk Single board + * + * Copyright (C) 2023-2024 Glider bv + */ + +#include "white-hawk-cpu-common.dtsi" +#include "white-hawk-common.dtsi" + +/ { + model = "Renesas White Hawk Single board"; + compatible = "renesas,white-hawk-single"; +}; + +&hscif0 { + uart-has-rtscts; +}; + +&hscif0_pins { + groups = "hscif0_data", "hscif0_ctrl"; + function = "hscif0"; +}; + +&pfc { + tsn0_pins: tsn0 { + mux { + groups = "tsn0_link", "tsn0_mdio", "tsn0_rgmii", + "tsn0_txcrefclk"; + function = "tsn0"; + }; + + link { + groups = "tsn0_link"; + bias-disable; + }; + + mdio { + groups = "tsn0_mdio"; + drive-strength = <24>; + bias-disable; + }; + + rgmii { + groups = "tsn0_rgmii"; + drive-strength = <24>; + bias-disable; + }; + }; +}; + +&tsn0 { + pinctrl-0 = <&tsn0_pins>; + pinctrl-names = "default"; + phy-mode = "rgmii"; + phy-handle = <&phy3>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + reset-gpios = <&gpio1 23 GPIO_ACTIVE_LOW>; + reset-post-delay-us = <4000>; + + phy3: ethernet-phy@0 { + compatible = "ethernet-phy-id002b.0980", + "ethernet-phy-ieee802.3-c22"; + reg = <0>; + interrupts-extended = <&gpio4 3 IRQ_TYPE_LEVEL_LOW>; + }; + }; +}; diff --git a/include/dt-bindings/clock/renesas,r9a09g047-cpg.h b/include/dt-bindings/clock/renesas,r9a09g047-cpg.h new file mode 100644 index 000000000000..1d031bf6bf03 --- /dev/null +++ b/include/dt-bindings/clock/renesas,r9a09g047-cpg.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) + * + * Copyright (C) 2024 Renesas Electronics Corp. + */ +#ifndef __DT_BINDINGS_CLOCK_RENESAS_R9A09G047_CPG_H__ +#define __DT_BINDINGS_CLOCK_RENESAS_R9A09G047_CPG_H__ + +#include <dt-bindings/clock/renesas-cpg-mssr.h> + +/* Core Clock list */ +#define R9A09G047_SYS_0_PCLK 0 +#define R9A09G047_CA55_0_CORECLK0 1 +#define R9A09G047_CA55_0_CORECLK1 2 +#define R9A09G047_CA55_0_CORECLK2 3 +#define R9A09G047_CA55_0_CORECLK3 4 +#define R9A09G047_CA55_0_PERIPHCLK 5 +#define R9A09G047_CM33_CLK0 6 +#define R9A09G047_CST_0_SWCLKTCK 7 +#define R9A09G047_IOTOP_0_SHCLK 8 + +#endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G047_CPG_H__ */ |