diff options
Diffstat (limited to '')
8 files changed, 163 insertions, 20 deletions
diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml index a1805b6e3f63..768bb3c2b456 100644 --- a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml @@ -26,6 +26,7 @@ properties: - renesas,r9a07g043-pinctrl # RZ/G2UL{Type-1,Type-2} and RZ/Five - renesas,r9a07g044-pinctrl # RZ/G2{L,LC} - renesas,r9a08g045-pinctrl # RZ/G3S + - renesas,r9a09g047-pinctrl # RZ/G3E - renesas,r9a09g057-pinctrl # RZ/V2H(P) - items: @@ -125,7 +126,7 @@ additionalProperties: drive-push-pull: true renesas,output-impedance: description: - Output impedance for pins on the RZ/V2H(P) SoC. The value provided by this + Output impedance for pins on the RZ/{G3E,V2H(P)} SoC. The value provided by this property corresponds to register bit values that can be set in the PFC_IOLH_mn register, which adjusts the drive strength value and is pin-dependent. $ref: /schemas/types.yaml#/definitions/uint32 @@ -142,7 +143,9 @@ allOf: properties: compatible: contains: - const: renesas,r9a09g057-pinctrl + enum: + - renesas,r9a09g047-pinctrl + - renesas,r9a09g057-pinctrl then: properties: resets: diff --git a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi index 61c6b8022ffd..104f740d20d3 100644 --- a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi @@ -2453,6 +2453,46 @@ }; }; + fcpvx0: fcp@fedb0000 { + compatible = "renesas,fcpv"; + reg = <0 0xfedb0000 0 0x200>; + clocks = <&cpg CPG_MOD 1100>; + power-domains = <&sysc R8A779G0_PD_A3ISP0>; + resets = <&cpg 1100>; + iommus = <&ipmmu_vi1 24>; + }; + + fcpvx1: fcp@fedb8000 { + compatible = "renesas,fcpv"; + reg = <0 0xfedb8000 0 0x200>; + clocks = <&cpg CPG_MOD 1101>; + power-domains = <&sysc R8A779G0_PD_A3ISP1>; + resets = <&cpg 1101>; + iommus = <&ipmmu_vi1 25>; + }; + + vspx0: vsp@fedd0000 { + compatible = "renesas,vsp2"; + reg = <0 0xfedd0000 0 0x8000>; + interrupts = <GIC_SPI 556 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 1028>; + power-domains = <&sysc R8A779G0_PD_A3ISP0>; + resets = <&cpg 1028>; + + renesas,fcp = <&fcpvx0>; + }; + + vspx1: vsp@fedd8000 { + compatible = "renesas,vsp2"; + reg = <0 0xfedd8000 0 0x8000>; + interrupts = <GIC_SPI 557 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 1029>; + power-domains = <&sysc R8A779G0_PD_A3ISP1>; + resets = <&cpg 1029>; + + renesas,fcp = <&fcpvx1>; + }; + prr: chipid@fff00044 { compatible = "renesas,prr"; reg = <0 0xfff00044 0 4>; diff --git a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi index 7a422e9ad29e..200e9ea89193 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi @@ -131,6 +131,19 @@ #size-cells = <2>; ranges; + pinctrl: pinctrl@10410000 { + compatible = "renesas,r9a09g047-pinctrl"; + reg = <0 0x10410000 0 0x10000>; + clocks = <&cpg CPG_CORE R9A09G047_IOTOP_0_SHCLK>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 0 232>; + #interrupt-cells = <2>; + interrupt-controller; + power-domains = <&cpg>; + resets = <&cpg 0xa5>, <&cpg 0xa6>; + }; + cpg: clock-controller@10420000 { compatible = "renesas,r9a09g047-cpg"; reg = <0 0x10420000 0 0x10000>; diff --git a/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts b/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts index d4d61bd03969..c063d47e2952 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts @@ -7,6 +7,7 @@ /dts-v1/; +#include <dt-bindings/pinctrl/renesas,r9a09g047-pinctrl.h> #include "r9a09g047e57.dtsi" #include "rzg3e-smarc-som.dtsi" #include "renesas-smarc2.dtsi" @@ -16,3 +17,15 @@ compatible = "renesas,smarc2-evk", "renesas,rzg3e-smarcm", "renesas,r9a09g047e57", "renesas,r9a09g047"; }; + +&pinctrl { + scif_pins: scif { + pins = "SCIF_TXD", "SCIF_RXD"; + renesas,output-impedance = <1>; + }; +}; + +&scif0 { + pinctrl-0 = <&scif_pins>; + pinctrl-names = "default"; +}; diff --git a/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts b/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts index 4703da8e9cff..0b705c987b6c 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts @@ -7,7 +7,7 @@ /dts-v1/; -#include <dt-bindings/pinctrl/rzg2l-pinctrl.h> +#include <dt-bindings/pinctrl/renesas,r9a09g057-pinctrl.h> #include <dt-bindings/gpio/gpio.h> #include "r9a09g057.dtsi" @@ -56,7 +56,7 @@ vqmmc_sdhi1: regulator-vccq-sdhi1 { compatible = "regulator-gpio"; regulator-name = "SDHI1 VccQ"; - gpios = <&pinctrl RZG2L_GPIO(10, 2) GPIO_ACTIVE_HIGH>; + gpios = <&pinctrl RZV2H_GPIO(A, 2) GPIO_ACTIVE_HIGH>; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; gpios-states = <0>; @@ -158,38 +158,38 @@ &pinctrl { i2c0_pins: i2c0 { - pinmux = <RZG2L_PORT_PINMUX(3, 0, 1)>, /* I2C0_SDA */ - <RZG2L_PORT_PINMUX(3, 1, 1)>; /* I2C0_SCL */ + pinmux = <RZV2H_PORT_PINMUX(3, 0, 1)>, /* I2C0_SDA */ + <RZV2H_PORT_PINMUX(3, 1, 1)>; /* I2C0_SCL */ }; i2c1_pins: i2c1 { - pinmux = <RZG2L_PORT_PINMUX(3, 2, 1)>, /* I2C1_SDA */ - <RZG2L_PORT_PINMUX(3, 3, 1)>; /* I2C1_SCL */ + pinmux = <RZV2H_PORT_PINMUX(3, 2, 1)>, /* I2C1_SDA */ + <RZV2H_PORT_PINMUX(3, 3, 1)>; /* I2C1_SCL */ }; i2c2_pins: i2c2 { - pinmux = <RZG2L_PORT_PINMUX(2, 0, 4)>, /* I2C2_SDA */ - <RZG2L_PORT_PINMUX(2, 1, 4)>; /* I2C2_SCL */ + pinmux = <RZV2H_PORT_PINMUX(2, 0, 4)>, /* I2C2_SDA */ + <RZV2H_PORT_PINMUX(2, 1, 4)>; /* I2C2_SCL */ }; i2c3_pins: i2c3 { - pinmux = <RZG2L_PORT_PINMUX(3, 6, 1)>, /* I2C3_SDA */ - <RZG2L_PORT_PINMUX(3, 7, 1)>; /* I2C3_SCL */ + pinmux = <RZV2H_PORT_PINMUX(3, 6, 1)>, /* I2C3_SDA */ + <RZV2H_PORT_PINMUX(3, 7, 1)>; /* I2C3_SCL */ }; i2c6_pins: i2c6 { - pinmux = <RZG2L_PORT_PINMUX(4, 4, 1)>, /* I2C6_SDA */ - <RZG2L_PORT_PINMUX(4, 5, 1)>; /* I2C6_SCL */ + pinmux = <RZV2H_PORT_PINMUX(4, 4, 1)>, /* I2C6_SDA */ + <RZV2H_PORT_PINMUX(4, 5, 1)>; /* I2C6_SCL */ }; i2c7_pins: i2c7 { - pinmux = <RZG2L_PORT_PINMUX(4, 6, 1)>, /* I2C7_SDA */ - <RZG2L_PORT_PINMUX(4, 7, 1)>; /* I2C7_SCL */ + pinmux = <RZV2H_PORT_PINMUX(4, 6, 1)>, /* I2C7_SDA */ + <RZV2H_PORT_PINMUX(4, 7, 1)>; /* I2C7_SCL */ }; i2c8_pins: i2c8 { - pinmux = <RZG2L_PORT_PINMUX(0, 6, 1)>, /* I2C8_SDA */ - <RZG2L_PORT_PINMUX(0, 7, 1)>; /* I2C8_SCL */ + pinmux = <RZV2H_PORT_PINMUX(0, 6, 1)>, /* I2C8_SDA */ + <RZV2H_PORT_PINMUX(0, 7, 1)>; /* I2C8_SCL */ }; scif_pins: scif { @@ -199,7 +199,7 @@ sd1-pwr-en-hog { gpio-hog; - gpios = <RZG2L_GPIO(10, 3) GPIO_ACTIVE_HIGH>; + gpios = <RZV2H_GPIO(A, 3) GPIO_ACTIVE_HIGH>; output-high; line-name = "sd1_pwr_en"; }; @@ -219,7 +219,7 @@ }; sd1_cd { - pinmux = <RZG2L_PORT_PINMUX(9, 4, 14)>; /* SD1_CD */ + pinmux = <RZV2H_PORT_PINMUX(9, 4, 14)>; /* SD1_CD */ }; }; }; diff --git a/arch/arm64/boot/dts/renesas/white-hawk-csi-dsi.dtsi b/arch/arm64/boot/dts/renesas/white-hawk-csi-dsi.dtsi index 3006b0a64f41..9017c4475a7c 100644 --- a/arch/arm64/boot/dts/renesas/white-hawk-csi-dsi.dtsi +++ b/arch/arm64/boot/dts/renesas/white-hawk-csi-dsi.dtsi @@ -21,6 +21,7 @@ bus-type = <MEDIA_BUS_TYPE_CSI2_CPHY>; clock-lanes = <0>; data-lanes = <1 2 3>; + line-orders = <0 3 0>; remote-endpoint = <&max96712_out0>; }; }; @@ -41,6 +42,7 @@ bus-type = <MEDIA_BUS_TYPE_CSI2_CPHY>; clock-lanes = <0>; data-lanes = <1 2 3>; + line-orders = <0 3 0>; remote-endpoint = <&max96712_out1>; }; }; diff --git a/include/dt-bindings/pinctrl/renesas,r9a09g047-pinctrl.h b/include/dt-bindings/pinctrl/renesas,r9a09g047-pinctrl.h new file mode 100644 index 000000000000..5917096720bd --- /dev/null +++ b/include/dt-bindings/pinctrl/renesas,r9a09g047-pinctrl.h @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * This header provides constants for Renesas RZ/G3E family pinctrl bindings. + * + * Copyright (C) 2024 Renesas Electronics Corp. + * + */ + +#ifndef __DT_BINDINGS_PINCTRL_RENESAS_R9A09G047_PINCTRL_H__ +#define __DT_BINDINGS_PINCTRL_RENESAS_R9A09G047_PINCTRL_H__ + +#include <dt-bindings/pinctrl/rzg2l-pinctrl.h> + +/* RZG3E_Px = Offset address of PFC_P_mn - 0x20 */ +#define RZG3E_P0 0 +#define RZG3E_P1 1 +#define RZG3E_P2 2 +#define RZG3E_P3 3 +#define RZG3E_P4 4 +#define RZG3E_P5 5 +#define RZG3E_P6 6 +#define RZG3E_P7 7 +#define RZG3E_P8 8 +#define RZG3E_PA 10 +#define RZG3E_PB 11 +#define RZG3E_PC 12 +#define RZG3E_PD 13 +#define RZG3E_PE 14 +#define RZG3E_PF 15 +#define RZG3E_PG 16 +#define RZG3E_PH 17 +#define RZG3E_PJ 19 +#define RZG3E_PK 20 +#define RZG3E_PL 21 +#define RZG3E_PM 22 +#define RZG3E_PS 28 + +#define RZG3E_PORT_PINMUX(b, p, f) RZG2L_PORT_PINMUX(RZG3E_P##b, p, f) +#define RZG3E_GPIO(port, pin) RZG2L_GPIO(RZG3E_P##port, pin) + +#endif /* __DT_BINDINGS_PINCTRL_RENESAS_R9A09G047_PINCTRL_H__ */ diff --git a/include/dt-bindings/pinctrl/renesas,r9a09g057-pinctrl.h b/include/dt-bindings/pinctrl/renesas,r9a09g057-pinctrl.h new file mode 100644 index 000000000000..2e83bf43160b --- /dev/null +++ b/include/dt-bindings/pinctrl/renesas,r9a09g057-pinctrl.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * This header provides constants for Renesas RZ/V2H family pinctrl bindings. + * + * Copyright (C) 2024 Renesas Electronics Corp. + * + */ + +#ifndef __DT_BINDINGS_PINCTRL_RENESAS_R9A09G057_PINCTRL_H__ +#define __DT_BINDINGS_PINCTRL_RENESAS_R9A09G057_PINCTRL_H__ + +#include <dt-bindings/pinctrl/rzg2l-pinctrl.h> + +/* RZV2H_Px = Offset address of PFC_P_mn - 0x20 */ +#define RZV2H_P0 0 +#define RZV2H_P1 1 +#define RZV2H_P2 2 +#define RZV2H_P3 3 +#define RZV2H_P4 4 +#define RZV2H_P5 5 +#define RZV2H_P6 6 +#define RZV2H_P7 7 +#define RZV2H_P8 8 +#define RZV2H_P9 9 +#define RZV2H_PA 10 +#define RZV2H_PB 11 + +#define RZV2H_PORT_PINMUX(b, p, f) RZG2L_PORT_PINMUX(RZV2H_P##b, p, f) +#define RZV2H_GPIO(port, pin) RZG2L_GPIO(RZV2H_P##port, pin) + +#endif /* __DT_BINDINGS_PINCTRL_RENESAS_R9A09G057_PINCTRL_H__ */ |