diff options
28 files changed, 392 insertions, 274 deletions
diff --git a/Documentation/devicetree/bindings/spi/mediatek,spi-mtk-nor.yaml b/Documentation/devicetree/bindings/spi/mediatek,spi-mtk-nor.yaml new file mode 100644 index 000000000000..42c9205ac991 --- /dev/null +++ b/Documentation/devicetree/bindings/spi/mediatek,spi-mtk-nor.yaml @@ -0,0 +1,85 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/spi/mediatek,spi-mtk-nor.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Serial NOR flash controller for MediaTek ARM SoCs + +maintainers: + - Bayi Cheng <bayi.cheng@mediatek.com> + - Chuanhong Guo <gch981213@gmail.com> + +description: | + This spi controller support single, dual, or quad mode transfer for + SPI NOR flash. There should be only one spi slave device following + generic spi bindings. It's not recommended to use this controller + for devices other than SPI NOR flash due to limited transfer + capability of this controller. + +allOf: + - $ref: /spi/spi-controller.yaml# + +properties: + compatible: + oneOf: + - items: + - enum: + - mediatek,mt2701-nor + - mediatek,mt2712-nor + - mediatek,mt7622-nor + - mediatek,mt7623-nor + - mediatek,mt7629-nor + - enum: + - mediatek,mt8173-nor + - items: + - const: mediatek,mt8173-nor + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: clock used for spi bus + - description: clock used for controller + + clock-names: + items: + - const: spi + - const: sf + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/mt8173-clk.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + + nor_flash: spi@1100d000 { + compatible = "mediatek,mt8173-nor"; + reg = <0 0x1100d000 0 0xe0>; + interrupts = <&spi_flash_irq>; + clocks = <&pericfg CLK_PERI_SPI>, <&topckgen CLK_TOP_SPINFI_IFR_SEL>; + clock-names = "spi", "sf"; + #address-cells = <1>; + #size-cells = <0>; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + }; + }; + }; + diff --git a/Documentation/devicetree/bindings/spi/renesas,rspi.yaml b/Documentation/devicetree/bindings/spi/renesas,rspi.yaml index c54ac059043f..0d201ce1d5da 100644 --- a/Documentation/devicetree/bindings/spi/renesas,rspi.yaml +++ b/Documentation/devicetree/bindings/spi/renesas,rspi.yaml @@ -25,6 +25,7 @@ properties: - items: - enum: + - renesas,qspi-r8a7742 # RZ/G1H - renesas,qspi-r8a7743 # RZ/G1M - renesas,qspi-r8a7744 # RZ/G1N - renesas,qspi-r8a7745 # RZ/G1E diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml index c62cbe79f00d..c79c8a167c46 100644 --- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml +++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml @@ -36,6 +36,8 @@ properties: - mscc,ocelot-spi - mscc,jaguar2-spi - const: snps,dw-apb-ssi + - description: Microchip Sparx5 SoC SPI Controller + const: microchip,sparx5-spi - description: Amazon Alpine SPI Controller const: amazon,alpine-dw-apb-ssi - description: Renesas RZ/N1 SPI Controller @@ -93,6 +95,12 @@ properties: - const: tx - const: rx + rx-sample-delay-ns: + default: 0 + description: Default value of the rx-sample-delay-ns property. + This value will be used if the property is not explicitly defined + for a SPI slave device. See below. + patternProperties: "^.*@[0-9a-f]+$": type: object @@ -107,6 +115,13 @@ patternProperties: spi-tx-bus-width: const: 1 + rx-sample-delay-ns: + description: SPI Rx sample delay offset, unit is nanoseconds. + The delay from the default sample time before the actual + sample of the rxd input signal occurs. The "rx_sample_delay" + is an optional feature of the designware controller, and the + upper limit is also subject to controller configuration. + unevaluatedProperties: false required: @@ -129,5 +144,11 @@ examples: num-cs = <2>; cs-gpios = <&gpio0 13 0>, <&gpio0 14 0>; + rx-sample-delay-ns = <3>; + spi-flash@1 { + compatible = "spi-nand"; + reg = <1>; + rx-sample-delay-ns = <7>; + }; }; ... diff --git a/Documentation/devicetree/bindings/spi/spi-mtk-nor.txt b/Documentation/devicetree/bindings/spi/spi-mtk-nor.txt deleted file mode 100644 index 984ae7fd4f94..000000000000 --- a/Documentation/devicetree/bindings/spi/spi-mtk-nor.txt +++ /dev/null @@ -1,47 +0,0 @@ -* Serial NOR flash controller for MediaTek ARM SoCs - -Required properties: -- compatible: For mt8173, compatible should be "mediatek,mt8173-nor", - and it's the fallback compatible for other Soc. - For every other SoC, should contain both the SoC-specific compatible - string and "mediatek,mt8173-nor". - The possible values are: - "mediatek,mt2701-nor", "mediatek,mt8173-nor" - "mediatek,mt2712-nor", "mediatek,mt8173-nor" - "mediatek,mt7622-nor", "mediatek,mt8173-nor" - "mediatek,mt7623-nor", "mediatek,mt8173-nor" - "mediatek,mt7629-nor", "mediatek,mt8173-nor" - "mediatek,mt8173-nor" -- reg: physical base address and length of the controller's register -- interrupts: Interrupt number used by the controller. -- clocks: the phandle of the clocks needed by the nor controller -- clock-names: the names of the clocks - the clocks should be named "spi" and "sf". "spi" is used for spi bus, - and "sf" is used for controller, these are the clocks witch - hardware needs to enabling nor flash and nor flash controller. - See Documentation/devicetree/bindings/clock/clock-bindings.txt for details. -- #address-cells: should be <1> -- #size-cells: should be <0> - -There should be only one spi slave device following generic spi bindings. -It's not recommended to use this controller for devices other than SPI NOR -flash due to limited transfer capability of this controller. - -Example: - -nor_flash: spi@1100d000 { - compatible = "mediatek,mt8173-nor"; - reg = <0 0x1100d000 0 0xe0>; - interrupts = <&spi_flash_irq>; - clocks = <&pericfg CLK_PERI_SPI>, - <&topckgen CLK_TOP_SPINFI_IFR_SEL>; - clock-names = "spi", "sf"; - #address-cells = <1>; - #size-cells = <0>; - - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - }; -}; - diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index c6ea760ea5f0..f705b0484f5e 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -637,7 +637,7 @@ config SPI_QCOM_QSPI config SPI_QUP tristate "Qualcomm SPI controller with QUP interface" - depends on ARCH_QCOM || (ARM && COMPILE_TEST) + depends on ARCH_QCOM || COMPILE_TEST help Qualcomm Universal Peripheral (QUP) core is an AHB slave that provides a common data path (an output FIFO and an input FIFO) diff --git a/drivers/spi/spi-armada-3700.c b/drivers/spi/spi-armada-3700.c index fcde419e480c..46feafe4e201 100644 --- a/drivers/spi/spi-armada-3700.c +++ b/drivers/spi/spi-armada-3700.c @@ -848,7 +848,6 @@ static int a3700_spi_probe(struct platform_device *pdev) platform_set_drvdata(pdev, master); spi = spi_master_get_devdata(master); - memset(spi, 0, sizeof(struct a3700_spi)); spi->master = master; diff --git a/drivers/spi/spi-atmel.c b/drivers/spi/spi-atmel.c index 2cfe6253a784..7c68d5cdbdc6 100644 --- a/drivers/spi/spi-atmel.c +++ b/drivers/spi/spi-atmel.c @@ -513,9 +513,8 @@ static int atmel_spi_configure_dma(struct spi_master *master, master->dma_tx = dma_request_chan(dev, "tx"); if (IS_ERR(master->dma_tx)) { - err = PTR_ERR(master->dma_tx); - if (err != -EPROBE_DEFER) - dev_err(dev, "No TX DMA channel, DMA is disabled\n"); + err = dev_err_probe(dev, PTR_ERR(master->dma_tx), + "No TX DMA channel, DMA is disabled\n"); goto error_clear; } diff --git a/drivers/spi/spi-bcm2835.c b/drivers/spi/spi-bcm2835.c index c45d76c848c8..5519f1eda238 100644 --- a/drivers/spi/spi-bcm2835.c +++ b/drivers/spi/spi-bcm2835.c @@ -1319,11 +1319,8 @@ static int bcm2835_spi_probe(struct platform_device *pdev) bs->clk = devm_clk_get(&pdev->dev, NULL); if (IS_ERR(bs->clk)) { - err = PTR_ERR(bs->clk); - if (err == -EPROBE_DEFER) - dev_dbg(&pdev->dev, "could not get clk: %d\n", err); - else - dev_err(&pdev->dev, "could not get clk: %d\n", err); + err = dev_err_probe(&pdev->dev, PTR_ERR(bs->clk), + "could not get clk\n"); goto out_controller_put; } diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c index 1c1a9d17eec0..0e5e45951eb0 100644 --- a/drivers/spi/spi-cadence-quadspi.c +++ b/drivers/spi/spi-cadence-quadspi.c @@ -1117,11 +1117,8 @@ static int cqspi_request_mmap_dma(struct cqspi_st *cqspi) cqspi->rx_chan = dma_request_chan_by_mask(&mask); if (IS_ERR(cqspi->rx_chan)) { int ret = PTR_ERR(cqspi->rx_chan); - - if (ret != -EPROBE_DEFER) - dev_err(&cqspi->pdev->dev, "No Rx DMA available\n"); cqspi->rx_chan = NULL; - return ret; + return dev_err_probe(&cqspi->pdev->dev, ret, "No Rx DMA available\n"); } init_completion(&cqspi->rx_dma_complete); diff --git a/drivers/spi/spi-dw-core.c b/drivers/spi/spi-dw-core.c index 323c66c5db50..55afdcee7d2b 100644 --- a/drivers/spi/spi-dw-core.c +++ b/drivers/spi/spi-dw-core.c @@ -12,6 +12,7 @@ #include <linux/delay.h> #include <linux/slab.h> #include <linux/spi/spi.h> +#include <linux/of.h> #include "spi-dw.h" @@ -26,6 +27,8 @@ struct chip_data { u16 clk_div; /* baud rate divider */ u32 speed_hz; /* baud rate */ + + u32 rx_sample_dly; /* RX sample delay */ }; #ifdef CONFIG_DEBUG_FS @@ -52,6 +55,7 @@ static const struct debugfs_reg32 dw_spi_dbgfs_regs[] = { DW_SPI_DBGFS_REG("DMACR", DW_SPI_DMACR), DW_SPI_DBGFS_REG("DMATDLR", DW_SPI_DMATDLR), DW_SPI_DBGFS_REG("DMARDLR", DW_SPI_DMARDLR), + DW_SPI_DBGFS_REG("RX_SAMPLE_DLY", DW_SPI_RX_SAMPLE_DLY), }; static int dw_spi_debugfs_init(struct dw_spi *dws) @@ -328,6 +332,12 @@ static int dw_spi_transfer_one(struct spi_controller *master, if (master->can_dma && master->can_dma(master, spi, transfer)) dws->dma_mapped = master->cur_msg_mapped; + /* Update RX sample delay if required */ + if (dws->cur_rx_sample_dly != chip->rx_sample_dly) { + dw_writel(dws, DW_SPI_RX_SAMPLE_DLY, chip->rx_sample_dly); + dws->cur_rx_sample_dly = chip->rx_sample_dly; + } + /* For poll mode just disable all interrupts */ spi_mask_intr(dws, 0xff); @@ -380,10 +390,22 @@ static int dw_spi_setup(struct spi_device *spi) /* Only alloc on first setup */ chip = spi_get_ctldata(spi); if (!chip) { + struct dw_spi *dws = spi_controller_get_devdata(spi->controller); + u32 rx_sample_dly_ns; + chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL); if (!chip) return -ENOMEM; spi_set_ctldata(spi, chip); + /* Get specific / default rx-sample-delay */ + if (device_property_read_u32(&spi->dev, + "rx-sample-delay-ns", + &rx_sample_dly_ns) != 0) + /* Use default controller value */ + rx_sample_dly_ns = dws->def_rx_sample_dly_ns; + chip->rx_sample_dly = DIV_ROUND_CLOSEST(rx_sample_dly_ns, + NSEC_PER_SEC / + dws->max_freq); } chip->tmode = SPI_TMOD_TR; @@ -472,6 +494,10 @@ int dw_spi_add_host(struct device *dev, struct dw_spi *dws) if (dws->set_cs) master->set_cs = dws->set_cs; + /* Get default rx sample delay */ + device_property_read_u32(dev, "rx-sample-delay-ns", + &dws->def_rx_sample_dly_ns); + /* Basic HW init */ spi_hw_init(dev, dws); diff --git a/drivers/spi/spi-dw-mmio.c b/drivers/spi/spi-dw-mmio.c index 403403deae66..18772c0c9220 100644 --- a/drivers/spi/spi-dw-mmio.c +++ b/drivers/spi/spi-dw-mmio.c @@ -45,6 +45,9 @@ struct dw_spi_mmio { #define MSCC_SPI_MST_SW_MODE_SW_PIN_CTRL_MODE BIT(13) #define MSCC_SPI_MST_SW_MODE_SW_SPI_CS(x) (x << 5) +#define SPARX5_FORCE_ENA 0xa4 +#define SPARX5_FORCE_VAL 0xa8 + /* * For Keem Bay, CTRLR0[31] is used to select controller mode. * 0: SSI is slave @@ -54,7 +57,7 @@ struct dw_spi_mmio { struct dw_spi_mscc { struct regmap *syscon; - void __iomem *spi_mst; + void __iomem *spi_mst; /* Not sparx5 */ }; /* @@ -134,6 +137,70 @@ static int dw_spi_mscc_jaguar2_init(struct platform_device *pdev, JAGUAR2_IF_SI_OWNER_OFFSET); } +/* + * The Designware SPI controller (referred to as master in the + * documentation) automatically deasserts chip select when the tx fifo + * is empty. The chip selects then needs to be driven by a CS override + * register. enable is an active low signal. + */ +static void dw_spi_sparx5_set_cs(struct spi_device *spi, bool enable) +{ + struct dw_spi *dws = spi_master_get_devdata(spi->master); + struct dw_spi_mmio *dwsmmio = container_of(dws, struct dw_spi_mmio, dws); + struct dw_spi_mscc *dwsmscc = dwsmmio->priv; + u8 cs = spi->chip_select; + + if (!enable) { + /* CS override drive enable */ + regmap_write(dwsmscc->syscon, SPARX5_FORCE_ENA, 1); + /* Now set CSx enabled */ + regmap_write(dwsmscc->syscon, SPARX5_FORCE_VAL, ~BIT(cs)); + /* Allow settle */ + usleep_range(1, 5); + } else { + /* CS value */ + regmap_write(dwsmscc->syscon, SPARX5_FORCE_VAL, ~0); + /* Allow settle */ + usleep_range(1, 5); + /* CS override drive disable */ + regmap_write(dwsmscc->syscon, SPARX5_FORCE_ENA, 0); + } + + dw_spi_set_cs(spi, enable); +} + +static int dw_spi_mscc_sparx5_init(struct platform_device *pdev, + struct dw_spi_mmio *dwsmmio) +{ + const char *syscon_name = "microchip,sparx5-cpu-syscon"; + struct device *dev = &pdev->dev; + struct dw_spi_mscc *dwsmscc; + + if (!IS_ENABLED(CONFIG_SPI_MUX)) { + dev_err(dev, "This driver needs CONFIG_SPI_MUX\n"); + return -EOPNOTSUPP; + } + + dwsmscc = devm_kzalloc(dev, sizeof(*dwsmscc), GFP_KERNEL); + if (!dwsmscc) + return -ENOMEM; + + dwsmscc->syscon = + syscon_regmap_lookup_by_compatible(syscon_name); + if (IS_ERR(dwsmscc->syscon)) { + dev_err(dev, "No syscon map %s\n", syscon_name); + return PTR_ERR(dwsmscc->syscon); + } + + dwsmmio->dws.set_cs = dw_spi_sparx5_set_cs; + dwsmmio->priv = dwsmscc; + + /* Register hook to configure CTRLR0 */ + dwsmmio->dws.update_cr0 = dw_spi_update_cr0; + + return 0; +} + static int dw_spi_alpine_init(struct platform_device *pdev, struct dw_spi_mmio *dwsmmio) { @@ -297,6 +364,7 @@ static const struct of_device_id dw_spi_mmio_of_match[] = { { .compatible = "renesas,rzn1-spi", .data = dw_spi_dw_apb_init}, { .compatible = "snps,dwc-ssi-1.01a", .data = dw_spi_dwc_ssi_init}, { .compatible = "intel,keembay-ssi", .data = dw_spi_keembay_init}, + { .compatible = "microchip,sparx5-spi", dw_spi_mscc_sparx5_init}, { /* end of table */} }; MODULE_DEVICE_TABLE(of, dw_spi_mmio_of_match); diff --git a/drivers/spi/spi-dw.h b/drivers/spi/spi-dw.h index 151ba316619e..90dfd21622d6 100644 --- a/drivers/spi/spi-dw.h +++ b/drivers/spi/spi-dw.h @@ -34,6 +34,7 @@ #define DW_SPI_IDR 0x58 #define DW_SPI_VERSION 0x5c #define DW_SPI_DR 0x60 +#define DW_SPI_RX_SAMPLE_DLY 0xf0 #define DW_SPI_CS_OVERRIDE 0xf4 /* Bit fields in CTRLR0 */ @@ -140,6 +141,8 @@ struct dw_spi { u8 n_bytes; /* current is a 1/2 bytes op */ irqreturn_t (*transfer_handler)(struct dw_spi *dws); u32 current_freq; /* frequency in hz */ + u32 cur_rx_sample_dly; + u32 def_rx_sample_dly_ns; /* DMA info */ struct dma_chan *txchan; diff --git a/drivers/spi/spi-fsl-dspi.c b/drivers/spi/spi-fsl-dspi.c index 91c6affe139c..c739cc7e4561 100644 --- a/drivers/spi/spi-fsl-dspi.c +++ b/drivers/spi/spi-fsl-dspi.c @@ -53,7 +53,6 @@ #define SPI_SR 0x2c #define SPI_SR_TCFQF BIT(31) -#define SPI_SR_EOQF BIT(28) #define SPI_SR_TFUF BIT(27) #define SPI_SR_TFFF BIT(25) #define SPI_SR_CMDTCF BIT(23) @@ -62,7 +61,7 @@ #define SPI_SR_TFIWF BIT(18) #define SPI_SR_RFDF BIT(17) #define SPI_SR_CMDFFF BIT(16) -#define SPI_SR_CLEAR (SPI_SR_TCFQF | SPI_SR_EOQF | \ +#define SPI_SR_CLEAR (SPI_SR_TCFQF | \ SPI_SR_TFUF | SPI_SR_TFFF | \ SPI_SR_CMDTCF | SPI_SR_SPEF | \ SPI_SR_RFOF | SPI_SR_TFIWF | \ @@ -75,7 +74,6 @@ #define SPI_RSER 0x30 #define SPI_RSER_TCFQE BIT(31) -#define SPI_RSER_EOQFE BIT(28) #define SPI_RSER_CMDTCFE BIT(23) #define SPI_PUSHR 0x34 @@ -114,7 +112,6 @@ struct chip_data { }; enum dspi_trans_mode { - DSPI_EOQ_MODE = 0, DSPI_XSPI_MODE, DSPI_DMA_MODE, }; @@ -189,7 +186,7 @@ static const struct fsl_dspi_devtype_data devtype_data[] = { .fifo_size = 4, }, [MCF5441X] = { - .trans_mode = DSPI_EOQ_MODE, + .trans_mode = DSPI_DMA_MODE, .max_clock_factor = 8, .fifo_size = 16, }, @@ -671,11 +668,6 @@ static void ns_delay_scale(char *psc, char *sc, int delay_ns, } } -static void dspi_pushr_write(struct fsl_dspi *dspi) -{ - regmap_write(dspi->regmap, SPI_PUSHR, dspi_pop_tx_pushr(dspi)); -} - static void dspi_pushr_cmd_write(struct fsl_dspi *dspi, u16 cmd) { /* @@ -735,21 +727,6 @@ static void dspi_xspi_fifo_write(struct fsl_dspi *dspi, int num_words) } } -static void dspi_eoq_fifo_write(struct fsl_dspi *dspi, int num_words) -{ - u16 xfer_cmd = dspi->tx_cmd; - - /* Fill TX FIFO with as many transfers as possible */ - while (num_words--) { - dspi->tx_cmd = xfer_cmd; - /* Request EOQF for last transfer in FIFO */ - if (num_words == 0) - dspi->tx_cmd |= SPI_PUSHR_CMD_EOQ; - /* Write combined TX FIFO and CMD FIFO entry */ - dspi_pushr_write(dspi); - } -} - static u32 dspi_popr_read(struct fsl_dspi *dspi) { u32 rxdata = 0; @@ -818,7 +795,7 @@ no_accel: dspi->oper_word_size = DIV_ROUND_UP(dspi->oper_bits_per_word, 8); /* - * Update CTAR here (code is common for EOQ, XSPI and DMA modes). + * Update CTAR here (code is common for XSPI and DMA modes). * We will update CTARE in the portion specific to XSPI, when we * also know the preload value (DTCP). */ @@ -862,10 +839,7 @@ static void dspi_fifo_write(struct fsl_dspi *dspi) spi_take_timestamp_pre(dspi->ctlr, xfer, dspi->progress, !dspi->irq); - if (dspi->devtype_data->trans_mode == DSPI_EOQ_MODE) - dspi_eoq_fifo_write(dspi, num_words); - else - dspi_xspi_fifo_write(dspi, num_words); + dspi_xspi_fifo_write(dspi, num_words); /* * Everything after this point is in a potential race with the next * interrupt, so we must never use dspi->words_in_flight again since it @@ -898,7 +872,7 @@ static int dspi_poll(struct fsl_dspi *dspi) regmap_read(dspi->regmap, SPI_SR, &spi_sr); regmap_write(dspi->regmap, SPI_SR, spi_sr); - if (spi_sr & (SPI_SR_EOQF | SPI_SR_CMDTCF)) + if (spi_sr & SPI_SR_CMDTCF) break; } while (--tries); @@ -916,7 +890,7 @@ static irqreturn_t dspi_interrupt(int irq, void *dev_id) regmap_read(dspi->regmap, SPI_SR, &spi_sr); regmap_write(dspi->regmap, SPI_SR, spi_sr); - if (!(spi_sr & (SPI_SR_EOQF | SPI_SR_CMDTCF))) + if (!(spi_sr & SPI_SR_CMDTCF)) return IRQ_NONE; if (dspi_rxtx(dspi) == 0) @@ -1204,9 +1178,6 @@ static int dspi_init(struct fsl_dspi *dspi) regmap_write(dspi->regmap, SPI_SR, SPI_SR_CLEAR); switch (dspi->devtype_data->trans_mode) { - case DSPI_EOQ_MODE: - regmap_write(dspi->regmap, SPI_RSER, SPI_RSER_EOQFE); - break; case DSPI_XSPI_MODE: regmap_write(dspi->regmap, SPI_RSER, SPI_RSER_CMDTCFE); break; @@ -1245,22 +1216,6 @@ static int dspi_slave_abort(struct spi_master *master) return 0; } -/* - * EOQ mode will inevitably deassert its PCS signal on last word in a queue - * (hardware limitation), so we need to inform the spi_device that larger - * buffers than the FIFO size are going to have the chip select randomly - * toggling, so it has a chance to adapt its message sizes. - */ -static size_t dspi_max_message_size(struct spi_device *spi) -{ - struct fsl_dspi *dspi = spi_controller_get_devdata(spi->controller); - - if (dspi->devtype_data->trans_mode == DSPI_EOQ_MODE) - return dspi->devtype_data->fifo_size; - - return SIZE_MAX; -} - static int dspi_probe(struct platform_device *pdev) { struct device_node *np = pdev->dev.of_node; @@ -1283,7 +1238,6 @@ static int dspi_probe(struct platform_device *pdev) ctlr->setup = dspi_setup; ctlr->transfer_one_message = dspi_transfer_one_message; - ctlr->max_message_size = dspi_max_message_size; ctlr->dev.of_node = pdev->dev.of_node; ctlr->cleanup = dspi_cleanup; diff --git a/drivers/spi/spi-fsl-espi.c b/drivers/spi/spi-fsl-espi.c index e60581283a24..7e9b6f8d6243 100644 --- a/drivers/spi/spi-fsl-espi.c +++ b/drivers/spi/spi-fsl-espi.c @@ -730,7 +730,7 @@ static int fsl_espi_probe(struct device *dev, struct resource *mem, if (ret < 0) goto err_pm; - dev_info(dev, "at 0x%p (irq = %u)\n", espi->reg_base, irq); + dev_info(dev, "irq = %u\n", irq); pm_runtime_mark_last_busy(dev); pm_runtime_put_autosuspend(dev); diff --git a/drivers/spi/spi-fsl-lpspi.c b/drivers/spi/spi-fsl-lpspi.c index 85a5c952389a..986b9793fd3c 100644 --- a/drivers/spi/spi-fsl-lpspi.c +++ b/drivers/spi/spi-fsl-lpspi.c @@ -944,8 +944,7 @@ static int fsl_lpspi_remove(struct platform_device *pdev) return 0; } -#ifdef CONFIG_PM_SLEEP -static int fsl_lpspi_suspend(struct device *dev) +static int __maybe_unused fsl_lpspi_suspend(struct device *dev) { int ret; @@ -954,7 +953,7 @@ static int fsl_lpspi_suspend(struct device *dev) return ret; } -static int fsl_lpspi_resume(struct device *dev) +static int __maybe_unused fsl_lpspi_resume(struct device *dev) { int ret; @@ -968,7 +967,6 @@ static int fsl_lpspi_resume(struct device *dev) return 0; } -#endif /* CONFIG_PM_SLEEP */ static const struct dev_pm_ops fsl_lpspi_pm_ops = { SET_RUNTIME_PM_OPS(fsl_lpspi_runtime_suspend, diff --git a/drivers/spi/spi-imx.c b/drivers/spi/spi-imx.c index 38a5f1304cec..197f60632072 100644 --- a/drivers/spi/spi-imx.c +++ b/drivers/spi/spi-imx.c @@ -1695,7 +1695,7 @@ static int spi_imx_probe(struct platform_device *pdev) goto out_runtime_pm_put; if (ret < 0) - dev_err(&pdev->dev, "dma setup error %d, use pio\n", + dev_dbg(&pdev->dev, "dma setup error %d, use pio\n", ret); } @@ -1710,8 +1710,6 @@ static int spi_imx_probe(struct platform_device *pdev) goto out_runtime_pm_put; } - dev_info(&pdev->dev, "probed\n"); - pm_runtime_mark_last_busy(spi_imx->dev); pm_runtime_put_autosuspend(spi_imx->dev); diff --git a/drivers/spi/spi-mtk-nor.c b/drivers/spi/spi-mtk-nor.c index b08d8e9a8ee9..6e6ca2b8e6c8 100644 --- a/drivers/spi/spi-mtk-nor.c +++ b/drivers/spi/spi-mtk-nor.c @@ -211,25 +211,28 @@ static bool mtk_nor_supports_op(struct spi_mem *mem, if (op->cmd.buswidth != 1) return false; - /* DTR ops not supported. */ - if (op->cmd.dtr || op->addr.dtr || op->dummy.dtr || op->data.dtr) - return false; - if (op->cmd.nbytes != 1) - return false; - if ((op->addr.nbytes == 3) || (op->addr.nbytes == 4)) { - if ((op->data.dir == SPI_MEM_DATA_IN) && mtk_nor_match_read(op)) - return true; - else if (op->data.dir == SPI_MEM_DATA_OUT) - return (op->addr.buswidth == 1) && - (op->dummy.buswidth == 0) && - (op->data.buswidth == 1); + switch(op->data.dir) { + case SPI_MEM_DATA_IN: + if (!mtk_nor_match_read(op)) + return false; + break; + case SPI_MEM_DATA_OUT: + if ((op->addr.buswidth != 1) || + (op->dummy.nbytes != 0) || + (op->data.buswidth != 1)) + return false; + break; + default: + break; + } } len = op->cmd.nbytes + op->addr.nbytes + op->dummy.nbytes; if ((len > MTK_NOR_PRG_MAX_SIZE) || ((op->data.nbytes) && (len == MTK_NOR_PRG_MAX_SIZE))) return false; - return true; + + return spi_mem_default_supports_op(mem, op); } static void mtk_nor_setup_bus(struct mtk_nor *sp, const struct spi_mem_op *op) diff --git a/drivers/spi/spi-mux.c b/drivers/spi/spi-mux.c index cc9ef371db14..37dfc6e82804 100644 --- a/drivers/spi/spi-mux.c +++ b/drivers/spi/spi-mux.c @@ -139,9 +139,8 @@ static int spi_mux_probe(struct spi_device *spi) priv->mux = devm_mux_control_get(&spi->dev, NULL); if (IS_ERR(priv->mux)) { - ret = PTR_ERR(priv->mux); - if (ret != -EPROBE_DEFER) - dev_err(&spi->dev, "failed to get control-mux\n"); + ret = dev_err_probe(&spi->dev, PTR_ERR(priv->mux), + "failed to get control-mux\n"); goto err_put_ctlr; } diff --git a/drivers/spi/spi-qcom-qspi.c b/drivers/spi/spi-qcom-qspi.c index e5829c56650b..c50e6074b49c 100644 --- a/drivers/spi/spi-qcom-qspi.c +++ b/drivers/spi/spi-qcom-qspi.c @@ -494,9 +494,8 @@ static int qcom_qspi_probe(struct platform_device *pdev) ctrl->icc_path_cpu_to_qspi = devm_of_icc_get(dev, "qspi-config"); if (IS_ERR(ctrl->icc_path_cpu_to_qspi)) { - ret = PTR_ERR(ctrl->icc_path_cpu_to_qspi); - if (ret != -EPROBE_DEFER) - dev_err(dev, "Failed to get cpu path: %d\n", ret); + ret = dev_err_probe(dev, PTR_ERR(ctrl->icc_path_cpu_to_qspi), + "Failed to get cpu path\n"); goto exit_probe_master_put; } /* Set BW vote for register access */ diff --git a/drivers/spi/spi-rspi.c b/drivers/spi/spi-rspi.c index cbc2387d450c..e39fd38f5180 100644 --- a/drivers/spi/spi-rspi.c +++ b/drivers/spi/spi-rspi.c @@ -161,6 +161,7 @@ #define SPCMD_SPRW 0x0010 /* SPI Read/Write Access (Dual/Quad) */ #define SPCMD_SSLA(i) ((i) << 4) /* SSL Assert Signal Setting */ #define SPCMD_BRDV_MASK 0x000c /* Bit Rate Division Setting */ +#define SPCMD_BRDV(brdv) ((brdv) << 2) #define SPCMD_CPOL 0x0002 /* Clock Polarity Setting */ #define SPCMD_CPHA 0x0001 /* Clock Phase Setting */ @@ -242,24 +243,40 @@ struct spi_ops { int (*transfer_one)(struct spi_controller *ctlr, struct spi_device *spi, struct spi_transfer *xfer); u16 extra_mode_bits; + u16 min_div; + u16 max_div; u16 flags; u16 fifo_size; u8 num_hw_ss; }; +static void rspi_set_rate(struct rspi_data *rspi) +{ + unsigned long clksrc; + int brdv = 0, spbr; + + clksrc = clk_get_rate(rspi->clk); + spbr = DIV_ROUND_UP(clksrc, 2 * rspi->speed_hz) - 1; + while (spbr > 255 && brdv < 3) { + brdv++; + spbr = DIV_ROUND_UP(spbr + 1, 2) - 1; + } + + rspi_write8(rspi, clamp(spbr, 0, 255), RSPI_SPBR); + rspi->spcmd |= SPCMD_BRDV(brdv); + rspi->speed_hz = DIV_ROUND_UP(clksrc, (2U << brdv) * (spbr + 1)); +} + /* * functions for RSPI on legacy SH */ static int rspi_set_config_register(struct rspi_data *rspi, int access_size) { - int spbr; - /* Sets output mode, MOSI signal, and (optionally) loopback */ rspi_write8(rspi, rspi->sppcr, RSPI_SPPCR); /* Sets transfer bit rate */ - spbr = DIV_ROUND_UP(clk_get_rate(rspi->clk), 2 * rspi->speed_hz) - 1; - rspi_write8(rspi, clamp(spbr, 0, 255), RSPI_SPBR); + rspi_set_rate(rspi); /* Disable dummy transmission, set 16-bit word access, 1 frame */ rspi_write8(rspi, 0, RSPI_SPDCR); @@ -289,25 +306,11 @@ static int rspi_set_config_register(struct rspi_data *rspi, int access_size) */ static int rspi_rz_set_config_register(struct rspi_data *rspi, int access_size) { - int spbr; - int div = 0; - unsigned long clksrc; - /* Sets output mode, MOSI signal, and (optionally) loopback */ rspi_write8(rspi, rspi->sppcr, RSPI_SPPCR); - clksrc = clk_get_rate(rspi->clk); - while (div < 3) { - if (rspi->speed_hz >= clksrc/4) /* 4=(CLK/2)/2 */ - break; - div++; - clksrc /= 2; - } - /* Sets transfer bit rate */ - spbr = DIV_ROUND_UP(clksrc, 2 * rspi->speed_hz) - 1; - rspi_write8(rspi, clamp(spbr, 0, 255), RSPI_SPBR); - rspi->spcmd |= div << 2; + rspi_set_rate(rspi); /* Disable dummy transmission, set byte access */ rspi_write8(rspi, SPDCR_SPLBYTE, RSPI_SPDCR); @@ -334,14 +337,28 @@ static int rspi_rz_set_config_register(struct rspi_data *rspi, int access_size) */ static int qspi_set_config_register(struct rspi_data *rspi, int access_size) { - int spbr; + unsigned long clksrc; + int brdv = 0, spbr; /* Sets output mode, MOSI signal, and (optionally) loopback */ rspi_write8(rspi, rspi->sppcr, RSPI_SPPCR); /* Sets transfer bit rate */ - spbr = DIV_ROUND_UP(clk_get_rate(rspi->clk), 2 * rspi->speed_hz); - rspi_write8(rspi, clamp(spbr, 0, 255), RSPI_SPBR); + clksrc = clk_get_rate(rspi->clk); + if (rspi->speed_hz >= clksrc) { + spbr = 0; + rspi->speed_hz = clksrc; + } else { + spbr = DIV_ROUND_UP(clksrc, 2 * rspi->speed_hz); + while (spbr > 255 && brdv < 3) { + brdv++; + spbr = DIV_ROUND_UP(spbr, 2); + } + spbr = clamp(spbr, 0, 255); + rspi->speed_hz = DIV_ROUND_UP(clksrc, (2U << brdv) * spbr); + } + rspi_write8(rspi, spbr, RSPI_SPBR); + rspi->spcmd |= SPCMD_BRDV(brdv); /* Disable dummy transmission, set byte access */ rspi_write8(rspi, 0, RSPI_SPDCR); @@ -686,6 +703,8 @@ static int rspi_common_transfer(struct rspi_data *rspi, { int ret; + xfer->effective_speed_hz = rspi->speed_hz; + ret = rspi_dma_check_then_transfer(rspi, xfer); if (ret != -EAGAIN) return ret; @@ -841,6 +860,7 @@ static int qspi_transfer_one(struct spi_controller *ctlr, { struct rspi_data *rspi = spi_controller_get_devdata(ctlr); + xfer->effective_speed_hz = rspi->speed_hz; if (spi->mode & SPI_LOOP) { return qspi_transfer_out_in(rspi, xfer); } else if (xfer->tx_nbits > SPI_NBITS_SINGLE) { @@ -1163,6 +1183,8 @@ static int rspi_remove(struct platform_device *pdev) static const struct spi_ops rspi_ops = { .set_config_register = rspi_set_config_register, .transfer_one = rspi_transfer_one, + .min_div = 2, + .max_div = 4096, .flags = SPI_CONTROLLER_MUST_TX, .fifo_size = 8, .num_hw_ss = 2, @@ -1171,6 +1193,8 @@ static const struct spi_ops rspi_ops = { static const struct spi_ops rspi_rz_ops = { .set_config_register = rspi_rz_set_config_register, .transfer_one = rspi_rz_transfer_one, + .min_div = 2, + .max_div = 4096, .flags = SPI_CONTROLLER_MUST_RX | SPI_CONTROLLER_MUST_TX, .fifo_size = 8, /* 8 for TX, 32 for RX */ .num_hw_ss = 1, @@ -1181,6 +1205,8 @@ static const struct spi_ops qspi_ops = { .transfer_one = qspi_transfer_one, .extra_mode_bits = SPI_TX_DUAL | SPI_TX_QUAD | SPI_RX_DUAL | SPI_RX_QUAD, + .min_div = 1, + .max_div = 4080, .flags = SPI_CONTROLLER_MUST_RX | SPI_CONTROLLER_MUST_TX, .fifo_size = 32, .num_hw_ss = 1, @@ -1242,6 +1268,7 @@ static int rspi_probe(struct platform_device *pdev) int ret; const struct rspi_plat_data *rspi_pd; const struct spi_ops *ops; + unsigned long clksrc; ctlr = spi_alloc_master(&pdev->dev, sizeof(struct rspi_data)); if (ctlr == NULL) @@ -1261,13 +1288,6 @@ static int rspi_probe(struct platform_device *pdev) ctlr->num_chipselect = 2; /* default */ } - /* ops parameter check */ - if (!ops->set_config_register) { - dev_err(&pdev->dev, "there is no set_config_register\n"); - ret = -ENODEV; - goto error1; - } - rspi = spi_controller_get_devdata(ctlr); platform_set_drvdata(pdev, rspi); rspi->ops = ops; @@ -1301,6 +1321,9 @@ static int rspi_probe(struct platform_device *pdev) ctlr->unprepare_message = rspi_unprepare_message; ctlr->mode_bits = SPI_CPHA | SPI_CPOL | SPI_CS_HIGH | SPI_LSB_FIRST | SPI_LOOP | ops->extra_mode_bits; + clksrc = clk_get_rate(rspi->clk); + ctlr->min_speed_hz = DIV_ROUND_UP(clksrc, ops->max_div); + ctlr->max_speed_hz = DIV_ROUND_UP(clksrc, ops->min_div); ctlr->flags = ops->flags; ctlr->dev.of_node = pdev->dev.of_node; ctlr->use_gpio_descriptors = true; diff --git a/drivers/spi/spi-s3c24xx.c b/drivers/spi/spi-s3c24xx.c index 2cb3b611c294..7742170fca91 100644 --- a/drivers/spi/spi-s3c24xx.c +++ b/drivers/spi/spi-s3c24xx.c @@ -28,7 +28,7 @@ #include "spi-s3c24xx-fiq.h" /** - * s3c24xx_spi_devstate - per device data + * struct s3c24xx_spi_devstate - per device data * @hz: Last frequency calculated for @sppre field. * @mode: Last mode setting for the @spcon field. * @spcon: Value to write to the SPCON register. diff --git a/drivers/spi/spi-sprd.c b/drivers/spi/spi-sprd.c index 6678f1cbc566..0443fec3a6ab 100644 --- a/drivers/spi/spi-sprd.c +++ b/drivers/spi/spi-sprd.c @@ -563,11 +563,11 @@ static int sprd_spi_dma_request(struct sprd_spi *ss) ss->dma.dma_chan[SPRD_SPI_TX] = dma_request_chan(ss->dev, "tx_chn"); if (IS_ERR_OR_NULL(ss->dma.dma_chan[SPRD_SPI_TX])) { + dma_release_channel(ss->dma.dma_chan[SPRD_SPI_RX]); if (PTR_ERR(ss->dma.dma_chan[SPRD_SPI_TX]) == -EPROBE_DEFER) return PTR_ERR(ss->dma.dma_chan[SPRD_SPI_TX]); dev_err(ss->dev, "request TX DMA channel failed!\n"); - dma_release_channel(ss->dma.dma_chan[SPRD_SPI_RX]); return PTR_ERR(ss->dma.dma_chan[SPRD_SPI_TX]); } diff --git a/drivers/spi/spi-stm32.c b/drivers/spi/spi-stm32.c index d4b33b358a31..f0e594b2fee4 100644 --- a/drivers/spi/spi-stm32.c +++ b/drivers/spi/spi-stm32.c @@ -1857,9 +1857,7 @@ static int stm32_spi_probe(struct platform_device *pdev) spi->irq = platform_get_irq(pdev, 0); if (spi->irq <= 0) { - ret = spi->irq; - if (ret != -EPROBE_DEFER) - dev_err(&pdev->dev, "failed to get irq: %d\n", ret); + ret = dev_err_probe(&pdev->dev, spi->irq, "failed to get irq\n"); goto err_master_put; } ret = devm_request_threaded_irq(&pdev->dev, spi->irq, diff --git a/drivers/spi/spi-synquacer.c b/drivers/spi/spi-synquacer.c index ae17c99cce03..42e82dbe3d41 100644 --- a/drivers/spi/spi-synquacer.c +++ b/drivers/spi/spi-synquacer.c @@ -640,9 +640,8 @@ static int synquacer_spi_probe(struct platform_device *pdev) } if (IS_ERR(sspi->clk)) { - if (!(PTR_ERR(sspi->clk) == -EPROBE_DEFER)) - dev_err(&pdev->dev, "clock not found\n"); - ret = PTR_ERR(sspi->clk); + ret = dev_err_probe(&pdev->dev, PTR_ERR(sspi->clk), + "clock not found\n"); goto put_spi; } diff --git a/drivers/spi/spi-tegra114.c b/drivers/spi/spi-tegra114.c index c2c58871a947..ca6886aaa519 100644 --- a/drivers/spi/spi-tegra114.c +++ b/drivers/spi/spi-tegra114.c @@ -664,16 +664,11 @@ static int tegra_spi_init_dma_param(struct tegra_spi_data *tspi, struct dma_chan *dma_chan; u32 *dma_buf; dma_addr_t dma_phys; - int ret; dma_chan = dma_request_chan(tspi->dev, dma_to_memory ? "rx" : "tx"); - if (IS_ERR(dma_chan)) { - ret = PTR_ERR(dma_chan); - if (ret != -EPROBE_DEFER) - dev_err(tspi->dev, - "Dma channel is not available: %d\n", ret); - return ret; - } + if (IS_ERR(dma_chan)) + return dev_err_probe(tspi->dev, PTR_ERR(dma_chan), + "Dma channel is not available\n"); dma_buf = dma_alloc_coherent(tspi->dev, tspi->dma_buf_size, &dma_phys, GFP_KERNEL); diff --git a/drivers/spi/spi-tegra20-slink.c b/drivers/spi/spi-tegra20-slink.c index a07b72e9c344..a0810765d4e5 100644 --- a/drivers/spi/spi-tegra20-slink.c +++ b/drivers/spi/spi-tegra20-slink.c @@ -600,13 +600,9 @@ static int tegra_slink_init_dma_param(struct tegra_slink_data *tspi, struct dma_slave_config dma_sconfig; dma_chan = dma_request_chan(tspi->dev, dma_to_memory ? "rx" : "tx"); - if (IS_ERR(dma_chan)) { - ret = PTR_ERR(dma_chan); - if (ret != -EPROBE_DEFER) - dev_err(tspi->dev, - "Dma channel is not available: %d\n", ret); - return ret; - } + if (IS_ERR(dma_chan)) + return dev_err_probe(tspi->dev, PTR_ERR(dma_chan), + "Dma channel is not available\n"); dma_buf = dma_alloc_coherent(tspi->dev, tspi->dma_buf_size, &dma_phys, GFP_KERNEL); diff --git a/drivers/spi/spidev.c b/drivers/spi/spidev.c index 455e99c4958e..859910ec8d9f 100644 --- a/drivers/spi/spidev.c +++ b/drivers/spi/spidev.c @@ -146,7 +146,7 @@ static ssize_t spidev_read(struct file *filp, char __user *buf, size_t count, loff_t *f_pos) { struct spidev_data *spidev; - ssize_t status = 0; + ssize_t status; /* chipselect only toggles at start or end of operation */ if (count > bufsiz) @@ -176,7 +176,7 @@ spidev_write(struct file *filp, const char __user *buf, size_t count, loff_t *f_pos) { struct spidev_data *spidev; - ssize_t status = 0; + ssize_t status; unsigned long missing; /* chipselect only toggles at start or end of operation */ diff --git a/include/linux/pxa2xx_ssp.h b/include/linux/pxa2xx_ssp.h index 6facf27865f9..7f73b26ed22e 100644 --- a/include/linux/pxa2xx_ssp.h +++ b/include/linux/pxa2xx_ssp.h @@ -1,7 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * pxa2xx_ssp.h - * * Copyright (C) 2003 Russell King, All Rights Reserved. * * This driver supports the following PXA CPU/SSP ports:- @@ -16,10 +14,16 @@ #ifndef __LINUX_SSP_H #define __LINUX_SSP_H -#include <linux/list.h> +#include <linux/bits.h> +#include <linux/compiler_types.h> #include <linux/io.h> -#include <linux/of.h> +#include <linux/kconfig.h> +#include <linux/list.h> +#include <linux/types.h> +struct clk; +struct device; +struct device_node; /* * SSP Serial Port Registers @@ -43,130 +47,127 @@ #define SSACDD (0x40) /* SSP Audio Clock Dither Divider */ /* Common PXA2xx bits first */ -#define SSCR0_DSS (0x0000000f) /* Data Size Select (mask) */ +#define SSCR0_DSS GENMASK(3, 0) /* Data Size Select (mask) */ #define SSCR0_DataSize(x) ((x) - 1) /* Data Size Select [4..16] */ -#define SSCR0_FRF (0x00000030) /* FRame Format (mask) */ +#define SSCR0_FRF GENMASK(5, 4) /* FRame Format (mask) */ #define SSCR0_Motorola (0x0 << 4) /* Motorola's Serial Peripheral Interface (SPI) */ #define SSCR0_TI (0x1 << 4) /* Texas Instruments' Synchronous Serial Protocol (SSP) */ #define SSCR0_National (0x2 << 4) /* National Microwire */ -#define SSCR0_ECS (1 << 6) /* External clock select */ -#define SSCR0_SSE (1 << 7) /* Synchronous Serial Port Enable */ +#define SSCR0_ECS BIT(6) /* External clock select */ +#define SSCR0_SSE BIT(7) /* Synchronous Serial Port Enable */ #define SSCR0_SCR(x) ((x) << 8) /* Serial Clock Rate (mask) */ /* PXA27x, PXA3xx */ -#define SSCR0_EDSS (1 << 20) /* Extended data size select */ -#define SSCR0_NCS (1 << 21) /* Network clock select */ -#define SSCR0_RIM (1 << 22) /* Receive FIFO overrrun interrupt mask */ -#define SSCR0_TUM (1 << 23) /* Transmit FIFO underrun interrupt mask */ -#define SSCR0_FRDC (0x07000000) /* Frame rate divider control (mask) */ +#define SSCR0_EDSS BIT(20) /* Extended data size select */ +#define SSCR0_NCS BIT(21) /* Network clock select */ +#define SSCR0_RIM BIT(22) /* Receive FIFO overrrun interrupt mask */ +#define SSCR0_TUM BIT(23) /* Transmit FIFO underrun interrupt mask */ +#define SSCR0_FRDC GENMASK(26, 24) /* Frame rate divider control (mask) */ #define SSCR0_SlotsPerFrm(x) (((x) - 1) << 24) /* Time slots per frame [1..8] */ -#define SSCR0_FPCKE (1 << 29) /* FIFO packing enable */ -#define SSCR0_ACS (1 << 30) /* Audio clock select */ -#define SSCR0_MOD (1 << 31) /* Mode (normal or network) */ - - -#define SSCR1_RIE (1 << 0) /* Receive FIFO Interrupt Enable */ -#define SSCR1_TIE (1 << 1) /* Transmit FIFO Interrupt Enable */ -#define SSCR1_LBM (1 << 2) /* Loop-Back Mode */ -#define SSCR1_SPO (1 << 3) /* Motorola SPI SSPSCLK polarity setting */ -#define SSCR1_SPH (1 << 4) /* Motorola SPI SSPSCLK phase setting */ -#define SSCR1_MWDS (1 << 5) /* Microwire Transmit Data Size */ - -#define SSSR_ALT_FRM_MASK 3 /* Masks the SFRM signal number */ -#define SSSR_TNF (1 << 2) /* Transmit FIFO Not Full */ -#define SSSR_RNE (1 << 3) /* Receive FIFO Not Empty */ -#define SSSR_BSY (1 << 4) /* SSP Busy */ -#define SSSR_TFS (1 << 5) /* Transmit FIFO Service Request */ -#define SSSR_RFS (1 << 6) /* Receive FIFO Service Request */ -#define SSSR_ROR (1 << 7) /* Receive FIFO Overrun */ +#define SSCR0_FPCKE BIT(29) /* FIFO packing enable */ +#define SSCR0_ACS BIT(30) /* Audio clock select */ +#define SSCR0_MOD BIT(31) /* Mode (normal or network) */ + +#define SSCR1_RIE BIT(0) /* Receive FIFO Interrupt Enable */ +#define SSCR1_TIE BIT(1) /* Transmit FIFO Interrupt Enable */ +#define SSCR1_LBM BIT(2) /* Loop-Back Mode */ +#define SSCR1_SPO BIT(3) /* Motorola SPI SSPSCLK polarity setting */ +#define SSCR1_SPH BIT(4) /* Motorola SPI SSPSCLK phase setting */ +#define SSCR1_MWDS BIT(5) /* Microwire Transmit Data Size */ + +#define SSSR_ALT_FRM_MASK GENMASK(1, 0) /* Masks the SFRM signal number */ +#define SSSR_TNF BIT(2) /* Transmit FIFO Not Full */ +#define SSSR_RNE BIT(3) /* Receive FIFO Not Empty */ +#define SSSR_BSY BIT(4) /* SSP Busy */ +#define SSSR_TFS BIT(5) /* Transmit FIFO Service Request */ +#define SSSR_RFS BIT(6) /* Receive FIFO Service Request */ +#define SSSR_ROR BIT(7) /* Receive FIFO Overrun */ #define RX_THRESH_DFLT 8 #define TX_THRESH_DFLT 8 -#define SSSR_TFL_MASK (0xf << 8) /* Transmit FIFO Level mask */ -#define SSSR_RFL_MASK (0xf << 12) /* Receive FIFO Level mask */ +#define SSSR_TFL_MASK GENMASK(11, 8) /* Transmit FIFO Level mask */ +#define SSSR_RFL_MASK GENMASK(15, 12) /* Receive FIFO Level mask */ -#define SSCR1_TFT (0x000003c0) /* Transmit FIFO Threshold (mask) */ +#define SSCR1_TFT GENMASK(9, 6) /* Transmit FIFO Threshold (mask) */ #define SSCR1_TxTresh(x) (((x) - 1) << 6) /* level [1..16] */ -#define SSCR1_RFT (0x00003c00) /* Receive FIFO Threshold (mask) */ +#define SSCR1_RFT GENMASK(13, 10) /* Receive FIFO Threshold (mask) */ #define SSCR1_RxTresh(x) (((x) - 1) << 10) /* level [1..16] */ #define RX_THRESH_CE4100_DFLT 2 #define TX_THRESH_CE4100_DFLT 2 -#define CE4100_SSSR_TFL_MASK (0x3 << 8) /* Transmit FIFO Level mask */ -#define CE4100_SSSR_RFL_MASK (0x3 << 12) /* Receive FIFO Level mask */ +#define CE4100_SSSR_TFL_MASK GENMASK(9, 8) /* Transmit FIFO Level mask */ +#define CE4100_SSSR_RFL_MASK GENMASK(13, 12) /* Receive FIFO Level mask */ -#define CE4100_SSCR1_TFT (0x000000c0) /* Transmit FIFO Threshold (mask) */ +#define CE4100_SSCR1_TFT GENMASK(7, 6) /* Transmit FIFO Threshold (mask) */ #define CE4100_SSCR1_TxTresh(x) (((x) - 1) << 6) /* level [1..4] */ -#define CE4100_SSCR1_RFT (0x00000c00) /* Receive FIFO Threshold (mask) */ +#define CE4100_SSCR1_RFT GENMASK(11, 10) /* Receive FIFO Threshold (mask) */ #define CE4100_SSCR1_RxTresh(x) (((x) - 1) << 10) /* level [1..4] */ /* QUARK_X1000 SSCR0 bit definition */ -#define QUARK_X1000_SSCR0_DSS (0x1F << 0) /* Data Size Select (mask) */ +#define QUARK_X1000_SSCR0_DSS GENMASK(4, 0) /* Data Size Select (mask) */ #define QUARK_X1000_SSCR0_DataSize(x) ((x) - 1) /* Data Size Select [4..32] */ -#define QUARK_X1000_SSCR0_FRF (0x3 << 5) /* FRame Format (mask) */ +#define QUARK_X1000_SSCR0_FRF GENMASK(6, 5) /* FRame Format (mask) */ #define QUARK_X1000_SSCR0_Motorola (0x0 << 5) /* Motorola's Serial Peripheral Interface (SPI) */ #define RX_THRESH_QUARK_X1000_DFLT 1 #define TX_THRESH_QUARK_X1000_DFLT 16 -#define QUARK_X1000_SSSR_TFL_MASK (0x1F << 8) /* Transmit FIFO Level mask */ -#define QUARK_X1000_SSSR_RFL_MASK (0x1F << 13) /* Receive FIFO Level mask */ +#define QUARK_X1000_SSSR_TFL_MASK GENMASK(12, 8) /* Transmit FIFO Level mask */ +#define QUARK_X1000_SSSR_RFL_MASK GENMASK(17, 13) /* Receive FIFO Level mask */ -#define QUARK_X1000_SSCR1_TFT (0x1F << 6) /* Transmit FIFO Threshold (mask) */ +#define QUARK_X1000_SSCR1_TFT GENMASK(10, 6) /* Transmit FIFO Threshold (mask) */ #define QUARK_X1000_SSCR1_TxTresh(x) (((x) - 1) << 6) /* level [1..32] */ -#define QUARK_X1000_SSCR1_RFT (0x1F << 11) /* Receive FIFO Threshold (mask) */ +#define QUARK_X1000_SSCR1_RFT GENMASK(15, 11) /* Receive FIFO Threshold (mask) */ #define QUARK_X1000_SSCR1_RxTresh(x) (((x) - 1) << 11) /* level [1..32] */ -#define QUARK_X1000_SSCR1_STRF (1 << 17) /* Select FIFO or EFWR */ -#define QUARK_X1000_SSCR1_EFWR (1 << 16) /* Enable FIFO Write/Read */ +#define QUARK_X1000_SSCR1_EFWR BIT(16) /* Enable FIFO Write/Read */ +#define QUARK_X1000_SSCR1_STRF BIT(17) /* Select FIFO or EFWR */ /* extra bits in PXA255, PXA26x and PXA27x SSP ports */ #define SSCR0_TISSP (1 << 4) /* TI Sync Serial Protocol */ #define SSCR0_PSP (3 << 4) /* PSP - Programmable Serial Protocol */ -#define SSCR1_TTELP (1 << 31) /* TXD Tristate Enable Last Phase */ -#define SSCR1_TTE (1 << 30) /* TXD Tristate Enable */ -#define SSCR1_EBCEI (1 << 29) /* Enable Bit Count Error interrupt */ -#define SSCR1_SCFR (1 << 28) /* Slave Clock free Running */ -#define SSCR1_ECRA (1 << 27) /* Enable Clock Request A */ -#define SSCR1_ECRB (1 << 26) /* Enable Clock request B */ -#define SSCR1_SCLKDIR (1 << 25) /* Serial Bit Rate Clock Direction */ -#define SSCR1_SFRMDIR (1 << 24) /* Frame Direction */ -#define SSCR1_RWOT (1 << 23) /* Receive Without Transmit */ -#define SSCR1_TRAIL (1 << 22) /* Trailing Byte */ -#define SSCR1_TSRE (1 << 21) /* Transmit Service Request Enable */ -#define SSCR1_RSRE (1 << 20) /* Receive Service Request Enable */ -#define SSCR1_TINTE (1 << 19) /* Receiver Time-out Interrupt enable */ -#define SSCR1_PINTE (1 << 18) /* Peripheral Trailing Byte Interrupt Enable */ -#define SSCR1_IFS (1 << 16) /* Invert Frame Signal */ -#define SSCR1_STRF (1 << 15) /* Select FIFO or EFWR */ -#define SSCR1_EFWR (1 << 14) /* Enable FIFO Write/Read */ - -#define SSSR_BCE (1 << 23) /* Bit Count Error */ -#define SSSR_CSS (1 << 22) /* Clock Synchronisation Status */ -#define SSSR_TUR (1 << 21) /* Transmit FIFO Under Run */ -#define SSSR_EOC (1 << 20) /* End Of Chain */ -#define SSSR_TINT (1 << 19) /* Receiver Time-out Interrupt */ -#define SSSR_PINT (1 << 18) /* Peripheral Trailing Byte Interrupt */ +#define SSCR1_EFWR BIT(14) /* Enable FIFO Write/Read */ +#define SSCR1_STRF BIT(15) /* Select FIFO or EFWR */ +#define SSCR1_IFS BIT(16) /* Invert Frame Signal */ +#define SSCR1_PINTE BIT(18) /* Peripheral Trailing Byte Interrupt Enable */ +#define SSCR1_TINTE BIT(19) /* Receiver Time-out Interrupt enable */ +#define SSCR1_RSRE BIT(20) /* Receive Service Request Enable */ +#define SSCR1_TSRE BIT(21) /* Transmit Service Request Enable */ +#define SSCR1_TRAIL BIT(22) /* Trailing Byte */ +#define SSCR1_RWOT BIT(23) /* Receive Without Transmit */ +#define SSCR1_SFRMDIR BIT(24) /* Frame Direction */ +#define SSCR1_SCLKDIR BIT(25) /* Serial Bit Rate Clock Direction */ +#define SSCR1_ECRB BIT(26) /* Enable Clock request B */ +#define SSCR1_ECRA BIT(27) /* Enable Clock Request A */ +#define SSCR1_SCFR BIT(28) /* Slave Clock free Running */ +#define SSCR1_EBCEI BIT(29) /* Enable Bit Count Error interrupt */ +#define SSCR1_TTE BIT(30) /* TXD Tristate Enable */ +#define SSCR1_TTELP BIT(31) /* TXD Tristate Enable Last Phase */ + +#define SSSR_PINT BIT(18) /* Peripheral Trailing Byte Interrupt */ +#define SSSR_TINT BIT(19) /* Receiver Time-out Interrupt */ +#define SSSR_EOC BIT(20) /* End Of Chain */ +#define SSSR_TUR BIT(21) /* Transmit FIFO Under Run */ +#define SSSR_CSS BIT(22) /* Clock Synchronisation Status */ +#define SSSR_BCE BIT(23) /* Bit Count Error */ #define SSPSP_SCMODE(x) ((x) << 0) /* Serial Bit Rate Clock Mode */ -#define SSPSP_SFRMP (1 << 2) /* Serial Frame Polarity */ -#define SSPSP_ETDS (1 << 3) /* End of Transfer data State */ +#define SSPSP_SFRMP BIT(2) /* Serial Frame Polarity */ +#define SSPSP_ETDS BIT(3) /* End of Transfer data State */ #define SSPSP_STRTDLY(x) ((x) << 4) /* Start Delay */ #define SSPSP_DMYSTRT(x) ((x) << 7) /* Dummy Start */ #define SSPSP_SFRMDLY(x) ((x) << 9) /* Serial Frame Delay */ #define SSPSP_SFRMWDTH(x) ((x) << 16) /* Serial Frame Width */ #define SSPSP_DMYSTOP(x) ((x) << 23) /* Dummy Stop */ -#define SSPSP_FSRT (1 << 25) /* Frame Sync Relative Timing */ +#define SSPSP_FSRT BIT(25) /* Frame Sync Relative Timing */ /* PXA3xx */ #define SSPSP_EDMYSTRT(x) ((x) << 26) /* Extended Dummy Start */ #define SSPSP_EDMYSTOP(x) ((x) << 28) /* Extended Dummy Stop */ #define SSPSP_TIMING_MASK (0x7f8001f0) -#define SSACD_SCDB (1 << 3) /* SSPSYSCLK Divider Bypass */ -#define SSACD_ACPS(x) ((x) << 4) /* Audio clock PLL select */ #define SSACD_ACDS(x) ((x) << 0) /* Audio clock divider select */ #define SSACD_ACDS_1 (0) #define SSACD_ACDS_2 (1) @@ -174,18 +175,24 @@ #define SSACD_ACDS_8 (3) #define SSACD_ACDS_16 (4) #define SSACD_ACDS_32 (5) +#define SSACD_SCDB BIT(3) /* SSPSYSCLK Divider Bypass */ #define SSACD_SCDB_4X (0) #define SSACD_SCDB_1X (1) -#define SSACD_SCDX8 (1 << 7) /* SYSCLK division ratio select */ +#define SSACD_ACPS(x) ((x) << 4) /* Audio clock PLL select */ +#define SSACD_SCDX8 BIT(7) /* SYSCLK division ratio select */ /* LPSS SSP */ #define SSITF 0x44 /* TX FIFO trigger level */ +#define SSITF_TxHiThresh(x) (((x) - 1) << 0) #define SSITF_TxLoThresh(x) (((x) - 1) << 8) -#define SSITF_TxHiThresh(x) ((x) - 1) #define SSIRF 0x48 /* RX FIFO trigger level */ #define SSIRF_RxThresh(x) ((x) - 1) +/* LPT/WPT SSP */ +#define SSCR2 (0x40) /* SSP Command / Status 2 */ +#define SSPSP2 (0x44) /* SSP Programmable Serial Protocol 2 */ + enum pxa_ssp_type { SSP_UNDEFINED = 0, PXA25x_SSP, /* pxa 210, 250, 255, 26x */ |