diff options
Diffstat (limited to 'arch/mips/kernel')
| -rw-r--r-- | arch/mips/kernel/cevt-r4k.c | 4 | ||||
| -rw-r--r-- | arch/mips/kernel/cps-vec.S | 35 | ||||
| -rw-r--r-- | arch/mips/kernel/genex.S | 2 | ||||
| -rw-r--r-- | arch/mips/kernel/idle.c | 14 | ||||
| -rw-r--r-- | arch/mips/kernel/r2300_fpu.S | 4 | ||||
| -rw-r--r-- | arch/mips/kernel/r4k_fpu.S | 12 | ||||
| -rw-r--r-- | arch/mips/kernel/smp-cps.c | 10 | ||||
| -rw-r--r-- | arch/mips/kernel/vmlinux.lds.S | 1 | ||||
| -rw-r--r-- | arch/mips/kernel/vpe-mt.c | 7 |
9 files changed, 42 insertions, 47 deletions
diff --git a/arch/mips/kernel/cevt-r4k.c b/arch/mips/kernel/cevt-r4k.c index 32ec67c9ab67..368e8475870f 100644 --- a/arch/mips/kernel/cevt-r4k.c +++ b/arch/mips/kernel/cevt-r4k.c @@ -200,7 +200,7 @@ int c0_compare_int_usable(void) */ if (c0_compare_int_pending()) { cnt = read_c0_count(); - write_c0_compare(cnt); + write_c0_compare(cnt - 1); back_to_back_c0_hazard(); while (read_c0_count() < (cnt + COMPARE_INT_SEEN_TICKS)) if (!c0_compare_int_pending()) @@ -228,7 +228,7 @@ int c0_compare_int_usable(void) if (!c0_compare_int_pending()) return 0; cnt = read_c0_count(); - write_c0_compare(cnt); + write_c0_compare(cnt - 1); back_to_back_c0_hazard(); while (read_c0_count() < (cnt + COMPARE_INT_SEEN_TICKS)) if (!c0_compare_int_pending()) diff --git a/arch/mips/kernel/cps-vec.S b/arch/mips/kernel/cps-vec.S index 975343240148..8ef492da827f 100644 --- a/arch/mips/kernel/cps-vec.S +++ b/arch/mips/kernel/cps-vec.S @@ -13,6 +13,7 @@ #include <asm/mipsregs.h> #include <asm/mipsmtregs.h> #include <asm/pm.h> +#include <asm/smp-cps.h> #define GCR_CPC_BASE_OFS 0x0088 #define GCR_CL_COHERENCE_OFS 0x2008 @@ -80,25 +81,20 @@ nop .endm - /* Calculate an uncached address for the CM GCRs */ - .macro cmgcrb dest - .set push - .set noat - MFC0 $1, CP0_CMGCRBASE - PTR_SLL $1, $1, 4 - PTR_LI \dest, UNCAC_BASE - PTR_ADDU \dest, \dest, $1 - .set pop - .endm .balign 0x1000 LEAF(mips_cps_core_entry) /* - * These first 4 bytes will be patched by cps_smp_setup to load the - * CCA to use into register s0. + * These first several instructions will be patched by cps_smp_setup to load the + * CCA to use into register s0 and GCR base address to register s1. */ - .word 0 + .rept CPS_ENTRY_PATCH_INSNS + nop + .endr + + .global mips_cps_core_entry_patch_end +mips_cps_core_entry_patch_end: /* Check whether we're here due to an NMI */ mfc0 k0, CP0_STATUS @@ -121,8 +117,7 @@ not_nmi: mtc0 t0, CP0_STATUS /* Skip cache & coherence setup if we're already coherent */ - cmgcrb v1 - lw s7, GCR_CL_COHERENCE_OFS(v1) + lw s7, GCR_CL_COHERENCE_OFS(s1) bnez s7, 1f nop @@ -132,7 +127,7 @@ not_nmi: /* Enter the coherent domain */ li t0, 0xff - sw t0, GCR_CL_COHERENCE_OFS(v1) + sw t0, GCR_CL_COHERENCE_OFS(s1) ehb /* Set Kseg0 CCA to that in s0 */ @@ -305,8 +300,7 @@ LEAF(mips_cps_core_init) */ LEAF(mips_cps_get_bootcfg) /* Calculate a pointer to this cores struct core_boot_config */ - cmgcrb t0 - lw t0, GCR_CL_ID_OFS(t0) + lw t0, GCR_CL_ID_OFS(s1) li t1, COREBOOTCFG_SIZE mul t0, t0, t1 PTR_LA t1, mips_cps_core_bootcfg @@ -366,8 +360,9 @@ LEAF(mips_cps_boot_vpes) has_vp t0, 5f /* Find base address of CPC */ - cmgcrb t3 - PTR_L t1, GCR_CPC_BASE_OFS(t3) + PTR_LA t1, mips_gcr_base + PTR_L t1, 0(t1) + PTR_L t1, GCR_CPC_BASE_OFS(t1) PTR_LI t2, ~0x7fff and t1, t1, t2 PTR_LI t2, UNCAC_BASE diff --git a/arch/mips/kernel/genex.S b/arch/mips/kernel/genex.S index 3425df6019c0..b6de8e88c1bd 100644 --- a/arch/mips/kernel/genex.S +++ b/arch/mips/kernel/genex.S @@ -480,7 +480,7 @@ NESTED(nmi_handler, PT_SIZE, sp) .set push /* gas fails to assemble cfc1 for some archs (octeon).*/ \ .set mips1 - SET_HARDFLOAT + .set hardfloat cfc1 a1, fcr31 .set pop .endm diff --git a/arch/mips/kernel/idle.c b/arch/mips/kernel/idle.c index 53adcc1b2ed5..5abc8b7340f8 100644 --- a/arch/mips/kernel/idle.c +++ b/arch/mips/kernel/idle.c @@ -33,13 +33,13 @@ static void __cpuidle r3081_wait(void) { unsigned long cfg = read_c0_conf(); write_c0_conf(cfg | R30XX_CONF_HALT); - raw_local_irq_enable(); } void __cpuidle r4k_wait(void) { raw_local_irq_enable(); __r4k_wait(); + raw_local_irq_disable(); } /* @@ -57,7 +57,6 @@ void __cpuidle r4k_wait_irqoff(void) " .set arch=r4000 \n" " wait \n" " .set pop \n"); - raw_local_irq_enable(); } /* @@ -77,7 +76,6 @@ static void __cpuidle rm7k_wait_irqoff(void) " wait \n" " mtc0 $1, $12 # stalls until W stage \n" " .set pop \n"); - raw_local_irq_enable(); } /* @@ -103,6 +101,8 @@ static void __cpuidle au1k_wait(void) " nop \n" " .set pop \n" : : "r" (au1k_wait), "r" (c0status)); + + raw_local_irq_disable(); } static int __initdata nowait; @@ -241,18 +241,16 @@ void __init check_wait(void) } } -void arch_cpu_idle(void) +__cpuidle void arch_cpu_idle(void) { if (cpu_wait) cpu_wait(); - else - raw_local_irq_enable(); } #ifdef CONFIG_CPU_IDLE -int mips_cpuidle_wait_enter(struct cpuidle_device *dev, - struct cpuidle_driver *drv, int index) +__cpuidle int mips_cpuidle_wait_enter(struct cpuidle_device *dev, + struct cpuidle_driver *drv, int index) { arch_cpu_idle(); return index; diff --git a/arch/mips/kernel/r2300_fpu.S b/arch/mips/kernel/r2300_fpu.S index 2748c55820c2..6c745aa9e825 100644 --- a/arch/mips/kernel/r2300_fpu.S +++ b/arch/mips/kernel/r2300_fpu.S @@ -64,7 +64,7 @@ LEAF(_restore_fp) */ LEAF(_save_fp_context) .set push - SET_HARDFLOAT + .set hardfloat li v0, 0 # assume success cfc1 t1, fcr31 EX2(s.d $f0, 0(a0)) @@ -98,7 +98,7 @@ LEAF(_save_fp_context) */ LEAF(_restore_fp_context) .set push - SET_HARDFLOAT + .set hardfloat li v0, 0 # assume success EX(lw t0, (a1)) EX2(l.d $f0, 0(a0)) diff --git a/arch/mips/kernel/r4k_fpu.S b/arch/mips/kernel/r4k_fpu.S index 2e687c60bc4f..4e8c98517d9d 100644 --- a/arch/mips/kernel/r4k_fpu.S +++ b/arch/mips/kernel/r4k_fpu.S @@ -26,7 +26,7 @@ .macro EX insn, reg, src .set push - SET_HARDFLOAT + .set hardfloat .set nomacro .ex\@: \insn \reg, \src .set pop @@ -98,14 +98,14 @@ LEAF(_init_msa_upper) */ LEAF(_save_fp_context) .set push - SET_HARDFLOAT + .set hardfloat cfc1 t1, fcr31 .set pop #if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPSR2) || \ defined(CONFIG_CPU_MIPSR5) || defined(CONFIG_CPU_MIPSR6) .set push - SET_HARDFLOAT + .set hardfloat #if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR5) .set mips32r2 .set fp=64 @@ -135,7 +135,7 @@ LEAF(_save_fp_context) #endif .set push - SET_HARDFLOAT + .set hardfloat /* Store the 16 even double precision registers */ EX sdc1 $f0, 0(a0) EX sdc1 $f2, 16(a0) @@ -173,7 +173,7 @@ LEAF(_restore_fp_context) #if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPSR2) || \ defined(CONFIG_CPU_MIPSR5) || defined(CONFIG_CPU_MIPSR6) .set push - SET_HARDFLOAT + .set hardfloat #if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR5) .set mips32r2 .set fp=64 @@ -201,7 +201,7 @@ LEAF(_restore_fp_context) 1: .set pop #endif .set push - SET_HARDFLOAT + .set hardfloat EX ldc1 $f0, 0(a0) EX ldc1 $f2, 16(a0) EX ldc1 $f4, 32(a0) diff --git a/arch/mips/kernel/smp-cps.c b/arch/mips/kernel/smp-cps.c index bcd6a944b839..4fc288bb85b9 100644 --- a/arch/mips/kernel/smp-cps.c +++ b/arch/mips/kernel/smp-cps.c @@ -162,6 +162,8 @@ static void __init cps_prepare_cpus(unsigned int max_cpus) */ entry_code = (u32 *)&mips_cps_core_entry; uasm_i_addiu(&entry_code, 16, 0, cca); + UASM_i_LA(&entry_code, 17, (long)mips_gcr_base); + BUG_ON((void *)entry_code > (void *)&mips_cps_core_entry_patch_end); blast_dcache_range((unsigned long)&mips_cps_core_entry, (unsigned long)entry_code); bc_wback_inv((unsigned long)&mips_cps_core_entry, @@ -424,9 +426,11 @@ static void cps_shutdown_this_cpu(enum cpu_death death) wmb(); } } else { - pr_debug("Gating power to core %d\n", core); - /* Power down the core */ - cps_pm_enter_state(CPS_PM_POWER_GATED); + if (IS_ENABLED(CONFIG_HOTPLUG_CPU)) { + pr_debug("Gating power to core %d\n", core); + /* Power down the core */ + cps_pm_enter_state(CPS_PM_POWER_GATED); + } } } diff --git a/arch/mips/kernel/vmlinux.lds.S b/arch/mips/kernel/vmlinux.lds.S index 1f98947fe715..52cbde60edf5 100644 --- a/arch/mips/kernel/vmlinux.lds.S +++ b/arch/mips/kernel/vmlinux.lds.S @@ -61,7 +61,6 @@ SECTIONS .text : { TEXT_TEXT SCHED_TEXT - CPUIDLE_TEXT LOCK_TEXT KPROBES_TEXT IRQENTRY_TEXT diff --git a/arch/mips/kernel/vpe-mt.c b/arch/mips/kernel/vpe-mt.c index 84a82b551ec3..223d6274f2e5 100644 --- a/arch/mips/kernel/vpe-mt.c +++ b/arch/mips/kernel/vpe-mt.c @@ -92,12 +92,11 @@ int vpe_run(struct vpe *v) write_tc_c0_tchalt(read_tc_c0_tchalt() & ~TCHALT_H); /* - * The sde-kit passes 'memsize' to __start in $a3, so set something - * here... Or set $a3 to zero and define DFLT_STACK_SIZE and - * DFLT_HEAP_SIZE when you compile your program + * We don't pass the memsize here, so VPE programs need to be + * compiled with DFLT_STACK_SIZE and DFLT_HEAP_SIZE defined. */ + mttgpr(7, 0); mttgpr(6, v->ntcs); - mttgpr(7, physical_memsize); /* set up VPE1 */ /* |