diff options
Diffstat (limited to 'drivers/clk/clk-hsdk-pll.c')
| -rw-r--r-- | drivers/clk/clk-hsdk-pll.c | 70 |
1 files changed, 39 insertions, 31 deletions
diff --git a/drivers/clk/clk-hsdk-pll.c b/drivers/clk/clk-hsdk-pll.c index 97d1e8c35b71..b4f8852201cb 100644 --- a/drivers/clk/clk-hsdk-pll.c +++ b/drivers/clk/clk-hsdk-pll.c @@ -53,35 +53,38 @@ struct hsdk_pll_cfg { u32 fbdiv; u32 odiv; u32 band; + u32 bypass; }; static const struct hsdk_pll_cfg asdt_pll_cfg[] = { - { 100000000, 0, 11, 3, 0 }, - { 133000000, 0, 15, 3, 0 }, - { 200000000, 1, 47, 3, 0 }, - { 233000000, 1, 27, 2, 0 }, - { 300000000, 1, 35, 2, 0 }, - { 333000000, 1, 39, 2, 0 }, - { 400000000, 1, 47, 2, 0 }, - { 500000000, 0, 14, 1, 0 }, - { 600000000, 0, 17, 1, 0 }, - { 700000000, 0, 20, 1, 0 }, - { 800000000, 0, 23, 1, 0 }, - { 900000000, 1, 26, 0, 0 }, - { 1000000000, 1, 29, 0, 0 }, - { 1100000000, 1, 32, 0, 0 }, - { 1200000000, 1, 35, 0, 0 }, - { 1300000000, 1, 38, 0, 0 }, - { 1400000000, 1, 41, 0, 0 }, - { 1500000000, 1, 44, 0, 0 }, - { 1600000000, 1, 47, 0, 0 }, + { 100000000, 0, 11, 3, 0, 0 }, + { 133000000, 0, 15, 3, 0, 0 }, + { 200000000, 1, 47, 3, 0, 0 }, + { 233000000, 1, 27, 2, 0, 0 }, + { 300000000, 1, 35, 2, 0, 0 }, + { 333000000, 1, 39, 2, 0, 0 }, + { 400000000, 1, 47, 2, 0, 0 }, + { 500000000, 0, 14, 1, 0, 0 }, + { 600000000, 0, 17, 1, 0, 0 }, + { 700000000, 0, 20, 1, 0, 0 }, + { 800000000, 0, 23, 1, 0, 0 }, + { 900000000, 1, 26, 0, 0, 0 }, + { 1000000000, 1, 29, 0, 0, 0 }, + { 1100000000, 1, 32, 0, 0, 0 }, + { 1200000000, 1, 35, 0, 0, 0 }, + { 1300000000, 1, 38, 0, 0, 0 }, + { 1400000000, 1, 41, 0, 0, 0 }, + { 1500000000, 1, 44, 0, 0, 0 }, + { 1600000000, 1, 47, 0, 0, 0 }, {} }; static const struct hsdk_pll_cfg hdmi_pll_cfg[] = { - { 297000000, 0, 21, 2, 0 }, - { 540000000, 0, 19, 1, 0 }, - { 594000000, 0, 21, 1, 0 }, + { 27000000, 0, 0, 0, 0, 1 }, + { 148500000, 0, 21, 3, 0, 0 }, + { 297000000, 0, 21, 2, 0, 0 }, + { 540000000, 0, 19, 1, 0, 0 }, + { 594000000, 0, 21, 1, 0, 0 }, {} }; @@ -134,11 +137,16 @@ static inline void hsdk_pll_set_cfg(struct hsdk_pll_clk *clk, { u32 val = 0; - /* Powerdown and Bypass bits should be cleared */ - val |= cfg->idiv << CGU_PLL_CTRL_IDIV_SHIFT; - val |= cfg->fbdiv << CGU_PLL_CTRL_FBDIV_SHIFT; - val |= cfg->odiv << CGU_PLL_CTRL_ODIV_SHIFT; - val |= cfg->band << CGU_PLL_CTRL_BAND_SHIFT; + if (cfg->bypass) { + val = hsdk_pll_read(clk, CGU_PLL_CTRL); + val |= CGU_PLL_CTRL_BYPASS; + } else { + /* Powerdown and Bypass bits should be cleared */ + val |= cfg->idiv << CGU_PLL_CTRL_IDIV_SHIFT; + val |= cfg->fbdiv << CGU_PLL_CTRL_FBDIV_SHIFT; + val |= cfg->odiv << CGU_PLL_CTRL_ODIV_SHIFT; + val |= cfg->band << CGU_PLL_CTRL_BAND_SHIFT; + } dev_dbg(clk->dev, "write configuration: %#x\n", val); @@ -172,14 +180,14 @@ static unsigned long hsdk_pll_recalc_rate(struct clk_hw *hw, dev_dbg(clk->dev, "current configuration: %#x\n", val); - /* Check if PLL is disabled */ - if (val & CGU_PLL_CTRL_PD) - return 0; - /* Check if PLL is bypassed */ if (val & CGU_PLL_CTRL_BYPASS) return parent_rate; + /* Check if PLL is disabled */ + if (val & CGU_PLL_CTRL_PD) + return 0; + /* input divider = reg.idiv + 1 */ idiv = 1 + ((val & CGU_PLL_CTRL_IDIV_MASK) >> CGU_PLL_CTRL_IDIV_SHIFT); /* fb divider = 2*(reg.fbdiv + 1) */ |