diff options
Diffstat (limited to 'drivers/hwtracing/coresight/coresight-tpdm.h')
| -rw-r--r-- | drivers/hwtracing/coresight/coresight-tpdm.h | 33 |
1 files changed, 21 insertions, 12 deletions
diff --git a/drivers/hwtracing/coresight/coresight-tpdm.h b/drivers/hwtracing/coresight/coresight-tpdm.h index e08d212642e3..b11754389734 100644 --- a/drivers/hwtracing/coresight/coresight-tpdm.h +++ b/drivers/hwtracing/coresight/coresight-tpdm.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2023-2025 Qualcomm Innovation Center, Inc. All rights reserved. */ #ifndef _CORESIGHT_CORESIGHT_TPDM_H @@ -9,7 +9,7 @@ /* The max number of the datasets that TPDM supports */ #define TPDM_DATASETS 7 -/* CMB Subunit Registers */ +/* CMB/MCMB Subunit Registers */ #define TPDM_CMB_CR (0xA00) /* CMB subunit timestamp insertion enable register */ #define TPDM_CMB_TIER (0xA04) @@ -28,6 +28,10 @@ #define TPDM_CMB_CR_ENA BIT(0) /* Trace collection mode for CMB subunit */ #define TPDM_CMB_CR_MODE BIT(1) +/* MCMB trigger lane select */ +#define TPDM_CMB_CR_XTRIG_LNSEL GENMASK(20, 18) +/* MCMB lane enablement */ +#define TPDM_CMB_CR_E_LN GENMASK(17, 10) /* Timestamp control for pattern match */ #define TPDM_CMB_TIER_PATT_TSENAB BIT(0) /* CMB CTI timestamp request */ @@ -41,6 +45,12 @@ /* MAX number of DSB MSR */ #define TPDM_CMB_MAX_MSR 32 +/* MAX lanes in the output pattern for MCMB configurations*/ +#define TPDM_MCMB_MAX_LANES 8 + +/* Filter bit 0~7 from the value for CR_E_LN */ +#define TPDM_MCMB_E_LN_MASK GENMASK(7, 0) + /* DSB Subunit Registers */ #define TPDM_DSB_CR (0x780) #define TPDM_DSB_TIER (0x784) @@ -112,11 +122,13 @@ * PERIPHIDR0[0] : Fix to 1 if ImplDef subunit present, else 0 * PERIPHIDR0[1] : Fix to 1 if DSB subunit present, else 0 * PERIPHIDR0[2] : Fix to 1 if CMB subunit present, else 0 + * PERIPHIDR0[6] : Fix to 1 if MCMB subunit present, else 0 */ #define TPDM_PIDR0_DS_IMPDEF BIT(0) #define TPDM_PIDR0_DS_DSB BIT(1) #define TPDM_PIDR0_DS_CMB BIT(2) +#define TPDM_PIDR0_DS_MCMB BIT(6) #define TPDM_DSB_MAX_LINES 256 /* MAX number of EDCR registers */ @@ -256,6 +268,9 @@ struct dsb_dataset { * @patt_ts: Indicates if pattern match for timestamp is enabled. * @trig_ts: Indicates if CTI trigger for timestamp is enabled. * @ts_all: Indicates if timestamp is enabled for all packets. + * struct mcmb_dataset + * @mcmb_trig_lane: Save data for trigger lane + * @mcmb_lane_select: Save data for lane enablement */ struct cmb_dataset { u32 trace_mode; @@ -267,6 +282,10 @@ struct cmb_dataset { bool patt_ts; bool trig_ts; bool ts_all; + struct { + u8 trig_lane; + u8 lane_select; + } mcmb; }; /** @@ -324,14 +343,4 @@ struct tpdm_dataset_attribute { enum dataset_mem mem; u32 idx; }; - -static bool tpdm_has_dsb_dataset(struct tpdm_drvdata *drvdata) -{ - return (drvdata->datasets & TPDM_PIDR0_DS_DSB); -} - -static bool tpdm_has_cmb_dataset(struct tpdm_drvdata *drvdata) -{ - return (drvdata->datasets & TPDM_PIDR0_DS_CMB); -} #endif /* _CORESIGHT_CORESIGHT_TPDM_H */ |