diff options
Diffstat (limited to 'drivers/misc/habanalabs/include/gaudi/asic_reg/tpc1_qm_regs.h')
| -rw-r--r-- | drivers/misc/habanalabs/include/gaudi/asic_reg/tpc1_qm_regs.h | 834 |
1 files changed, 834 insertions, 0 deletions
diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc1_qm_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc1_qm_regs.h new file mode 100644 index 000000000000..af10ef7a87d9 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc1_qm_regs.h @@ -0,0 +1,834 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_TPC1_QM_REGS_H_ +#define ASIC_REG_TPC1_QM_REGS_H_ + +/* + ***************************************** + * TPC1_QM (Prototype: QMAN) + ***************************************** + */ + +#define mmTPC1_QM_GLBL_CFG0 0xE48000 + +#define mmTPC1_QM_GLBL_CFG1 0xE48004 + +#define mmTPC1_QM_GLBL_PROT 0xE48008 + +#define mmTPC1_QM_GLBL_ERR_CFG 0xE4800C + +#define mmTPC1_QM_GLBL_SECURE_PROPS_0 0xE48010 + +#define mmTPC1_QM_GLBL_SECURE_PROPS_1 0xE48014 + +#define mmTPC1_QM_GLBL_SECURE_PROPS_2 0xE48018 + +#define mmTPC1_QM_GLBL_SECURE_PROPS_3 0xE4801C + +#define mmTPC1_QM_GLBL_SECURE_PROPS_4 0xE48020 + +#define mmTPC1_QM_GLBL_NON_SECURE_PROPS_0 0xE48024 + +#define mmTPC1_QM_GLBL_NON_SECURE_PROPS_1 0xE48028 + +#define mmTPC1_QM_GLBL_NON_SECURE_PROPS_2 0xE4802C + +#define mmTPC1_QM_GLBL_NON_SECURE_PROPS_3 0xE48030 + +#define mmTPC1_QM_GLBL_NON_SECURE_PROPS_4 0xE48034 + +#define mmTPC1_QM_GLBL_STS0 0xE48038 + +#define mmTPC1_QM_GLBL_STS1_0 0xE48040 + +#define mmTPC1_QM_GLBL_STS1_1 0xE48044 + +#define mmTPC1_QM_GLBL_STS1_2 0xE48048 + +#define mmTPC1_QM_GLBL_STS1_3 0xE4804C + +#define mmTPC1_QM_GLBL_STS1_4 0xE48050 + +#define mmTPC1_QM_GLBL_MSG_EN_0 0xE48054 + +#define mmTPC1_QM_GLBL_MSG_EN_1 0xE48058 + +#define mmTPC1_QM_GLBL_MSG_EN_2 0xE4805C + +#define mmTPC1_QM_GLBL_MSG_EN_3 0xE48060 + +#define mmTPC1_QM_GLBL_MSG_EN_4 0xE48068 + +#define mmTPC1_QM_PQ_BASE_LO_0 0xE48070 + +#define mmTPC1_QM_PQ_BASE_LO_1 0xE48074 + +#define mmTPC1_QM_PQ_BASE_LO_2 0xE48078 + +#define mmTPC1_QM_PQ_BASE_LO_3 0xE4807C + +#define mmTPC1_QM_PQ_BASE_HI_0 0xE48080 + +#define mmTPC1_QM_PQ_BASE_HI_1 0xE48084 + +#define mmTPC1_QM_PQ_BASE_HI_2 0xE48088 + +#define mmTPC1_QM_PQ_BASE_HI_3 0xE4808C + +#define mmTPC1_QM_PQ_SIZE_0 0xE48090 + +#define mmTPC1_QM_PQ_SIZE_1 0xE48094 + +#define mmTPC1_QM_PQ_SIZE_2 0xE48098 + +#define mmTPC1_QM_PQ_SIZE_3 0xE4809C + +#define mmTPC1_QM_PQ_PI_0 0xE480A0 + +#define mmTPC1_QM_PQ_PI_1 0xE480A4 + +#define mmTPC1_QM_PQ_PI_2 0xE480A8 + +#define mmTPC1_QM_PQ_PI_3 0xE480AC + +#define mmTPC1_QM_PQ_CI_0 0xE480B0 + +#define mmTPC1_QM_PQ_CI_1 0xE480B4 + +#define mmTPC1_QM_PQ_CI_2 0xE480B8 + +#define mmTPC1_QM_PQ_CI_3 0xE480BC + +#define mmTPC1_QM_PQ_CFG0_0 0xE480C0 + +#define mmTPC1_QM_PQ_CFG0_1 0xE480C4 + +#define mmTPC1_QM_PQ_CFG0_2 0xE480C8 + +#define mmTPC1_QM_PQ_CFG0_3 0xE480CC + +#define mmTPC1_QM_PQ_CFG1_0 0xE480D0 + +#define mmTPC1_QM_PQ_CFG1_1 0xE480D4 + +#define mmTPC1_QM_PQ_CFG1_2 0xE480D8 + +#define mmTPC1_QM_PQ_CFG1_3 0xE480DC + +#define mmTPC1_QM_PQ_ARUSER_31_11_0 0xE480E0 + +#define mmTPC1_QM_PQ_ARUSER_31_11_1 0xE480E4 + +#define mmTPC1_QM_PQ_ARUSER_31_11_2 0xE480E8 + +#define mmTPC1_QM_PQ_ARUSER_31_11_3 0xE480EC + +#define mmTPC1_QM_PQ_STS0_0 0xE480F0 + +#define mmTPC1_QM_PQ_STS0_1 0xE480F4 + +#define mmTPC1_QM_PQ_STS0_2 0xE480F8 + +#define mmTPC1_QM_PQ_STS0_3 0xE480FC + +#define mmTPC1_QM_PQ_STS1_0 0xE48100 + +#define mmTPC1_QM_PQ_STS1_1 0xE48104 + +#define mmTPC1_QM_PQ_STS1_2 0xE48108 + +#define mmTPC1_QM_PQ_STS1_3 0xE4810C + +#define mmTPC1_QM_CQ_CFG0_0 0xE48110 + +#define mmTPC1_QM_CQ_CFG0_1 0xE48114 + +#define mmTPC1_QM_CQ_CFG0_2 0xE48118 + +#define mmTPC1_QM_CQ_CFG0_3 0xE4811C + +#define mmTPC1_QM_CQ_CFG0_4 0xE48120 + +#define mmTPC1_QM_CQ_CFG1_0 0xE48124 + +#define mmTPC1_QM_CQ_CFG1_1 0xE48128 + +#define mmTPC1_QM_CQ_CFG1_2 0xE4812C + +#define mmTPC1_QM_CQ_CFG1_3 0xE48130 + +#define mmTPC1_QM_CQ_CFG1_4 0xE48134 + +#define mmTPC1_QM_CQ_ARUSER_31_11_0 0xE48138 + +#define mmTPC1_QM_CQ_ARUSER_31_11_1 0xE4813C + +#define mmTPC1_QM_CQ_ARUSER_31_11_2 0xE48140 + +#define mmTPC1_QM_CQ_ARUSER_31_11_3 0xE48144 + +#define mmTPC1_QM_CQ_ARUSER_31_11_4 0xE48148 + +#define mmTPC1_QM_CQ_STS0_0 0xE4814C + +#define mmTPC1_QM_CQ_STS0_1 0xE48150 + +#define mmTPC1_QM_CQ_STS0_2 0xE48154 + +#define mmTPC1_QM_CQ_STS0_3 0xE48158 + +#define mmTPC1_QM_CQ_STS0_4 0xE4815C + +#define mmTPC1_QM_CQ_STS1_0 0xE48160 + +#define mmTPC1_QM_CQ_STS1_1 0xE48164 + +#define mmTPC1_QM_CQ_STS1_2 0xE48168 + +#define mmTPC1_QM_CQ_STS1_3 0xE4816C + +#define mmTPC1_QM_CQ_STS1_4 0xE48170 + +#define mmTPC1_QM_CQ_PTR_LO_0 0xE48174 + +#define mmTPC1_QM_CQ_PTR_HI_0 0xE48178 + +#define mmTPC1_QM_CQ_TSIZE_0 0xE4817C + +#define mmTPC1_QM_CQ_CTL_0 0xE48180 + +#define mmTPC1_QM_CQ_PTR_LO_1 0xE48184 + +#define mmTPC1_QM_CQ_PTR_HI_1 0xE48188 + +#define mmTPC1_QM_CQ_TSIZE_1 0xE4818C + +#define mmTPC1_QM_CQ_CTL_1 0xE48190 + +#define mmTPC1_QM_CQ_PTR_LO_2 0xE48194 + +#define mmTPC1_QM_CQ_PTR_HI_2 0xE48198 + +#define mmTPC1_QM_CQ_TSIZE_2 0xE4819C + +#define mmTPC1_QM_CQ_CTL_2 0xE481A0 + +#define mmTPC1_QM_CQ_PTR_LO_3 0xE481A4 + +#define mmTPC1_QM_CQ_PTR_HI_3 0xE481A8 + +#define mmTPC1_QM_CQ_TSIZE_3 0xE481AC + +#define mmTPC1_QM_CQ_CTL_3 0xE481B0 + +#define mmTPC1_QM_CQ_PTR_LO_4 0xE481B4 + +#define mmTPC1_QM_CQ_PTR_HI_4 0xE481B8 + +#define mmTPC1_QM_CQ_TSIZE_4 0xE481BC + +#define mmTPC1_QM_CQ_CTL_4 0xE481C0 + +#define mmTPC1_QM_CQ_PTR_LO_STS_0 0xE481C4 + +#define mmTPC1_QM_CQ_PTR_LO_STS_1 0xE481C8 + +#define mmTPC1_QM_CQ_PTR_LO_STS_2 0xE481CC + +#define mmTPC1_QM_CQ_PTR_LO_STS_3 0xE481D0 + +#define mmTPC1_QM_CQ_PTR_LO_STS_4 0xE481D4 + +#define mmTPC1_QM_CQ_PTR_HI_STS_0 0xE481D8 + +#define mmTPC1_QM_CQ_PTR_HI_STS_1 0xE481DC + +#define mmTPC1_QM_CQ_PTR_HI_STS_2 0xE481E0 + +#define mmTPC1_QM_CQ_PTR_HI_STS_3 0xE481E4 + +#define mmTPC1_QM_CQ_PTR_HI_STS_4 0xE481E8 + +#define mmTPC1_QM_CQ_TSIZE_STS_0 0xE481EC + +#define mmTPC1_QM_CQ_TSIZE_STS_1 0xE481F0 + +#define mmTPC1_QM_CQ_TSIZE_STS_2 0xE481F4 + +#define mmTPC1_QM_CQ_TSIZE_STS_3 0xE481F8 + +#define mmTPC1_QM_CQ_TSIZE_STS_4 0xE481FC + +#define mmTPC1_QM_CQ_CTL_STS_0 0xE48200 + +#define mmTPC1_QM_CQ_CTL_STS_1 0xE48204 + +#define mmTPC1_QM_CQ_CTL_STS_2 0xE48208 + +#define mmTPC1_QM_CQ_CTL_STS_3 0xE4820C + +#define mmTPC1_QM_CQ_CTL_STS_4 0xE48210 + +#define mmTPC1_QM_CQ_IFIFO_CNT_0 0xE48214 + +#define mmTPC1_QM_CQ_IFIFO_CNT_1 0xE48218 + +#define mmTPC1_QM_CQ_IFIFO_CNT_2 0xE4821C + +#define mmTPC1_QM_CQ_IFIFO_CNT_3 0xE48220 + +#define mmTPC1_QM_CQ_IFIFO_CNT_4 0xE48224 + +#define mmTPC1_QM_CP_MSG_BASE0_ADDR_LO_0 0xE48228 + +#define mmTPC1_QM_CP_MSG_BASE0_ADDR_LO_1 0xE4822C + +#define mmTPC1_QM_CP_MSG_BASE0_ADDR_LO_2 0xE48230 + +#define mmTPC1_QM_CP_MSG_BASE0_ADDR_LO_3 0xE48234 + +#define mmTPC1_QM_CP_MSG_BASE0_ADDR_LO_4 0xE48238 + +#define mmTPC1_QM_CP_MSG_BASE0_ADDR_HI_0 0xE4823C + +#define mmTPC1_QM_CP_MSG_BASE0_ADDR_HI_1 0xE48240 + +#define mmTPC1_QM_CP_MSG_BASE0_ADDR_HI_2 0xE48244 + +#define mmTPC1_QM_CP_MSG_BASE0_ADDR_HI_3 0xE48248 + +#define mmTPC1_QM_CP_MSG_BASE0_ADDR_HI_4 0xE4824C + +#define mmTPC1_QM_CP_MSG_BASE1_ADDR_LO_0 0xE48250 + +#define mmTPC1_QM_CP_MSG_BASE1_ADDR_LO_1 0xE48254 + +#define mmTPC1_QM_CP_MSG_BASE1_ADDR_LO_2 0xE48258 + +#define mmTPC1_QM_CP_MSG_BASE1_ADDR_LO_3 0xE4825C + +#define mmTPC1_QM_CP_MSG_BASE1_ADDR_LO_4 0xE48260 + +#define mmTPC1_QM_CP_MSG_BASE1_ADDR_HI_0 0xE48264 + +#define mmTPC1_QM_CP_MSG_BASE1_ADDR_HI_1 0xE48268 + +#define mmTPC1_QM_CP_MSG_BASE1_ADDR_HI_2 0xE4826C + +#define mmTPC1_QM_CP_MSG_BASE1_ADDR_HI_3 0xE48270 + +#define mmTPC1_QM_CP_MSG_BASE1_ADDR_HI_4 0xE48274 + +#define mmTPC1_QM_CP_MSG_BASE2_ADDR_LO_0 0xE48278 + +#define mmTPC1_QM_CP_MSG_BASE2_ADDR_LO_1 0xE4827C + +#define mmTPC1_QM_CP_MSG_BASE2_ADDR_LO_2 0xE48280 + +#define mmTPC1_QM_CP_MSG_BASE2_ADDR_LO_3 0xE48284 + +#define mmTPC1_QM_CP_MSG_BASE2_ADDR_LO_4 0xE48288 + +#define mmTPC1_QM_CP_MSG_BASE2_ADDR_HI_0 0xE4828C + +#define mmTPC1_QM_CP_MSG_BASE2_ADDR_HI_1 0xE48290 + +#define mmTPC1_QM_CP_MSG_BASE2_ADDR_HI_2 0xE48294 + +#define mmTPC1_QM_CP_MSG_BASE2_ADDR_HI_3 0xE48298 + +#define mmTPC1_QM_CP_MSG_BASE2_ADDR_HI_4 0xE4829C + +#define mmTPC1_QM_CP_MSG_BASE3_ADDR_LO_0 0xE482A0 + +#define mmTPC1_QM_CP_MSG_BASE3_ADDR_LO_1 0xE482A4 + +#define mmTPC1_QM_CP_MSG_BASE3_ADDR_LO_2 0xE482A8 + +#define mmTPC1_QM_CP_MSG_BASE3_ADDR_LO_3 0xE482AC + +#define mmTPC1_QM_CP_MSG_BASE3_ADDR_LO_4 0xE482B0 + +#define mmTPC1_QM_CP_MSG_BASE3_ADDR_HI_0 0xE482B4 + +#define mmTPC1_QM_CP_MSG_BASE3_ADDR_HI_1 0xE482B8 + +#define mmTPC1_QM_CP_MSG_BASE3_ADDR_HI_2 0xE482BC + +#define mmTPC1_QM_CP_MSG_BASE3_ADDR_HI_3 0xE482C0 + +#define mmTPC1_QM_CP_MSG_BASE3_ADDR_HI_4 0xE482C4 + +#define mmTPC1_QM_CP_LDMA_TSIZE_OFFSET_0 0xE482C8 + +#define mmTPC1_QM_CP_LDMA_TSIZE_OFFSET_1 0xE482CC + +#define mmTPC1_QM_CP_LDMA_TSIZE_OFFSET_2 0xE482D0 + +#define mmTPC1_QM_CP_LDMA_TSIZE_OFFSET_3 0xE482D4 + +#define mmTPC1_QM_CP_LDMA_TSIZE_OFFSET_4 0xE482D8 + +#define mmTPC1_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 0xE482E0 + +#define mmTPC1_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 0xE482E4 + +#define mmTPC1_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 0xE482E8 + +#define mmTPC1_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 0xE482EC + +#define mmTPC1_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 0xE482F0 + +#define mmTPC1_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 0xE482F4 + +#define mmTPC1_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 0xE482F8 + +#define mmTPC1_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 0xE482FC + +#define mmTPC1_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 0xE48300 + +#define mmTPC1_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 0xE48304 + +#define mmTPC1_QM_CP_FENCE0_RDATA_0 0xE48308 + +#define mmTPC1_QM_CP_FENCE0_RDATA_1 0xE4830C + +#define mmTPC1_QM_CP_FENCE0_RDATA_2 0xE48310 + +#define mmTPC1_QM_CP_FENCE0_RDATA_3 0xE48314 + +#define mmTPC1_QM_CP_FENCE0_RDATA_4 0xE48318 + +#define mmTPC1_QM_CP_FENCE1_RDATA_0 0xE4831C + +#define mmTPC1_QM_CP_FENCE1_RDATA_1 0xE48320 + +#define mmTPC1_QM_CP_FENCE1_RDATA_2 0xE48324 + +#define mmTPC1_QM_CP_FENCE1_RDATA_3 0xE48328 + +#define mmTPC1_QM_CP_FENCE1_RDATA_4 0xE4832C + +#define mmTPC1_QM_CP_FENCE2_RDATA_0 0xE48330 + +#define mmTPC1_QM_CP_FENCE2_RDATA_1 0xE48334 + +#define mmTPC1_QM_CP_FENCE2_RDATA_2 0xE48338 + +#define mmTPC1_QM_CP_FENCE2_RDATA_3 0xE4833C + +#define mmTPC1_QM_CP_FENCE2_RDATA_4 0xE48340 + +#define mmTPC1_QM_CP_FENCE3_RDATA_0 0xE48344 + +#define mmTPC1_QM_CP_FENCE3_RDATA_1 0xE48348 + +#define mmTPC1_QM_CP_FENCE3_RDATA_2 0xE4834C + +#define mmTPC1_QM_CP_FENCE3_RDATA_3 0xE48350 + +#define mmTPC1_QM_CP_FENCE3_RDATA_4 0xE48354 + +#define mmTPC1_QM_CP_FENCE0_CNT_0 0xE48358 + +#define mmTPC1_QM_CP_FENCE0_CNT_1 0xE4835C + +#define mmTPC1_QM_CP_FENCE0_CNT_2 0xE48360 + +#define mmTPC1_QM_CP_FENCE0_CNT_3 0xE48364 + +#define mmTPC1_QM_CP_FENCE0_CNT_4 0xE48368 + +#define mmTPC1_QM_CP_FENCE1_CNT_0 0xE4836C + +#define mmTPC1_QM_CP_FENCE1_CNT_1 0xE48370 + +#define mmTPC1_QM_CP_FENCE1_CNT_2 0xE48374 + +#define mmTPC1_QM_CP_FENCE1_CNT_3 0xE48378 + +#define mmTPC1_QM_CP_FENCE1_CNT_4 0xE4837C + +#define mmTPC1_QM_CP_FENCE2_CNT_0 0xE48380 + +#define mmTPC1_QM_CP_FENCE2_CNT_1 0xE48384 + +#define mmTPC1_QM_CP_FENCE2_CNT_2 0xE48388 + +#define mmTPC1_QM_CP_FENCE2_CNT_3 0xE4838C + +#define mmTPC1_QM_CP_FENCE2_CNT_4 0xE48390 + +#define mmTPC1_QM_CP_FENCE3_CNT_0 0xE48394 + +#define mmTPC1_QM_CP_FENCE3_CNT_1 0xE48398 + +#define mmTPC1_QM_CP_FENCE3_CNT_2 0xE4839C + +#define mmTPC1_QM_CP_FENCE3_CNT_3 0xE483A0 + +#define mmTPC1_QM_CP_FENCE3_CNT_4 0xE483A4 + +#define mmTPC1_QM_CP_STS_0 0xE483A8 + +#define mmTPC1_QM_CP_STS_1 0xE483AC + +#define mmTPC1_QM_CP_STS_2 0xE483B0 + +#define mmTPC1_QM_CP_STS_3 0xE483B4 + +#define mmTPC1_QM_CP_STS_4 0xE483B8 + +#define mmTPC1_QM_CP_CURRENT_INST_LO_0 0xE483BC + +#define mmTPC1_QM_CP_CURRENT_INST_LO_1 0xE483C0 + +#define mmTPC1_QM_CP_CURRENT_INST_LO_2 0xE483C4 + +#define mmTPC1_QM_CP_CURRENT_INST_LO_3 0xE483C8 + +#define mmTPC1_QM_CP_CURRENT_INST_LO_4 0xE483CC + +#define mmTPC1_QM_CP_CURRENT_INST_HI_0 0xE483D0 + +#define mmTPC1_QM_CP_CURRENT_INST_HI_1 0xE483D4 + +#define mmTPC1_QM_CP_CURRENT_INST_HI_2 0xE483D8 + +#define mmTPC1_QM_CP_CURRENT_INST_HI_3 0xE483DC + +#define mmTPC1_QM_CP_CURRENT_INST_HI_4 0xE483E0 + +#define mmTPC1_QM_CP_BARRIER_CFG_0 0xE483F4 + +#define mmTPC1_QM_CP_BARRIER_CFG_1 0xE483F8 + +#define mmTPC1_QM_CP_BARRIER_CFG_2 0xE483FC + +#define mmTPC1_QM_CP_BARRIER_CFG_3 0xE48400 + +#define mmTPC1_QM_CP_BARRIER_CFG_4 0xE48404 + +#define mmTPC1_QM_CP_DBG_0_0 0xE48408 + +#define mmTPC1_QM_CP_DBG_0_1 0xE4840C + +#define mmTPC1_QM_CP_DBG_0_2 0xE48410 + +#define mmTPC1_QM_CP_DBG_0_3 0xE48414 + +#define mmTPC1_QM_CP_DBG_0_4 0xE48418 + +#define mmTPC1_QM_CP_ARUSER_31_11_0 0xE4841C + +#define mmTPC1_QM_CP_ARUSER_31_11_1 0xE48420 + +#define mmTPC1_QM_CP_ARUSER_31_11_2 0xE48424 + +#define mmTPC1_QM_CP_ARUSER_31_11_3 0xE48428 + +#define mmTPC1_QM_CP_ARUSER_31_11_4 0xE4842C + +#define mmTPC1_QM_CP_AWUSER_31_11_0 0xE48430 + +#define mmTPC1_QM_CP_AWUSER_31_11_1 0xE48434 + +#define mmTPC1_QM_CP_AWUSER_31_11_2 0xE48438 + +#define mmTPC1_QM_CP_AWUSER_31_11_3 0xE4843C + +#define mmTPC1_QM_CP_AWUSER_31_11_4 0xE48440 + +#define mmTPC1_QM_ARB_CFG_0 0xE48A00 + +#define mmTPC1_QM_ARB_CHOISE_Q_PUSH 0xE48A04 + +#define mmTPC1_QM_ARB_WRR_WEIGHT_0 0xE48A08 + +#define mmTPC1_QM_ARB_WRR_WEIGHT_1 0xE48A0C + +#define mmTPC1_QM_ARB_WRR_WEIGHT_2 0xE48A10 + +#define mmTPC1_QM_ARB_WRR_WEIGHT_3 0xE48A14 + +#define mmTPC1_QM_ARB_CFG_1 0xE48A18 + +#define mmTPC1_QM_ARB_MST_AVAIL_CRED_0 0xE48A20 + +#define mmTPC1_QM_ARB_MST_AVAIL_CRED_1 0xE48A24 + +#define mmTPC1_QM_ARB_MST_AVAIL_CRED_2 0xE48A28 + +#define mmTPC1_QM_ARB_MST_AVAIL_CRED_3 0xE48A2C + +#define mmTPC1_QM_ARB_MST_AVAIL_CRED_4 0xE48A30 + +#define mmTPC1_QM_ARB_MST_AVAIL_CRED_5 0xE48A34 + +#define mmTPC1_QM_ARB_MST_AVAIL_CRED_6 0xE48A38 + +#define mmTPC1_QM_ARB_MST_AVAIL_CRED_7 0xE48A3C + +#define mmTPC1_QM_ARB_MST_AVAIL_CRED_8 0xE48A40 + +#define mmTPC1_QM_ARB_MST_AVAIL_CRED_9 0xE48A44 + +#define mmTPC1_QM_ARB_MST_AVAIL_CRED_10 0xE48A48 + +#define mmTPC1_QM_ARB_MST_AVAIL_CRED_11 0xE48A4C + +#define mmTPC1_QM_ARB_MST_AVAIL_CRED_12 0xE48A50 + +#define mmTPC1_QM_ARB_MST_AVAIL_CRED_13 0xE48A54 + +#define mmTPC1_QM_ARB_MST_AVAIL_CRED_14 0xE48A58 + +#define mmTPC1_QM_ARB_MST_AVAIL_CRED_15 0xE48A5C + +#define mmTPC1_QM_ARB_MST_AVAIL_CRED_16 0xE48A60 + +#define mmTPC1_QM_ARB_MST_AVAIL_CRED_17 0xE48A64 + +#define mmTPC1_QM_ARB_MST_AVAIL_CRED_18 0xE48A68 + +#define mmTPC1_QM_ARB_MST_AVAIL_CRED_19 0xE48A6C + +#define mmTPC1_QM_ARB_MST_AVAIL_CRED_20 0xE48A70 + +#define mmTPC1_QM_ARB_MST_AVAIL_CRED_21 0xE48A74 + +#define mmTPC1_QM_ARB_MST_AVAIL_CRED_22 0xE48A78 + +#define mmTPC1_QM_ARB_MST_AVAIL_CRED_23 0xE48A7C + +#define mmTPC1_QM_ARB_MST_AVAIL_CRED_24 0xE48A80 + +#define mmTPC1_QM_ARB_MST_AVAIL_CRED_25 0xE48A84 + +#define mmTPC1_QM_ARB_MST_AVAIL_CRED_26 0xE48A88 + +#define mmTPC1_QM_ARB_MST_AVAIL_CRED_27 0xE48A8C + +#define mmTPC1_QM_ARB_MST_AVAIL_CRED_28 0xE48A90 + +#define mmTPC1_QM_ARB_MST_AVAIL_CRED_29 0xE48A94 + +#define mmTPC1_QM_ARB_MST_AVAIL_CRED_30 0xE48A98 + +#define mmTPC1_QM_ARB_MST_AVAIL_CRED_31 0xE48A9C + +#define mmTPC1_QM_ARB_MST_CRED_INC 0xE48AA0 + +#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_0 0xE48AA4 + +#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_1 0xE48AA8 + +#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_2 0xE48AAC + +#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_3 0xE48AB0 + +#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_4 0xE48AB4 + +#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_5 0xE48AB8 + +#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_6 0xE48ABC + +#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_7 0xE48AC0 + +#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_8 0xE48AC4 + +#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_9 0xE48AC8 + +#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_10 0xE48ACC + +#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_11 0xE48AD0 + +#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_12 0xE48AD4 + +#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_13 0xE48AD8 + +#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_14 0xE48ADC + +#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_15 0xE48AE0 + +#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_16 0xE48AE4 + +#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_17 0xE48AE8 + +#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_18 0xE48AEC + +#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_19 0xE48AF0 + +#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_20 0xE48AF4 + +#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_21 0xE48AF8 + +#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_22 0xE48AFC + +#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_23 0xE48B00 + +#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_24 0xE48B04 + +#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_25 0xE48B08 + +#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_26 0xE48B0C + +#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_27 0xE48B10 + +#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_28 0xE48B14 + +#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_29 0xE48B18 + +#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_30 0xE48B1C + +#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_31 0xE48B20 + +#define mmTPC1_QM_ARB_SLV_MASTER_INC_CRED_OFST 0xE48B28 + +#define mmTPC1_QM_ARB_MST_SLAVE_EN 0xE48B2C + +#define mmTPC1_QM_ARB_MST_QUIET_PER 0xE48B34 + +#define mmTPC1_QM_ARB_SLV_CHOISE_WDT 0xE48B38 + +#define mmTPC1_QM_ARB_SLV_ID 0xE48B3C + +#define mmTPC1_QM_ARB_MSG_MAX_INFLIGHT 0xE48B44 + +#define mmTPC1_QM_ARB_MSG_AWUSER_31_11 0xE48B48 + +#define mmTPC1_QM_ARB_MSG_AWUSER_SEC_PROP 0xE48B4C + +#define mmTPC1_QM_ARB_MSG_AWUSER_NON_SEC_PROP 0xE48B50 + +#define mmTPC1_QM_ARB_BASE_LO 0xE48B54 + +#define mmTPC1_QM_ARB_BASE_HI 0xE48B58 + +#define mmTPC1_QM_ARB_STATE_STS 0xE48B80 + +#define mmTPC1_QM_ARB_CHOISE_FULLNESS_STS 0xE48B84 + +#define mmTPC1_QM_ARB_MSG_STS 0xE48B88 + +#define mmTPC1_QM_ARB_SLV_CHOISE_Q_HEAD 0xE48B8C + +#define mmTPC1_QM_ARB_ERR_CAUSE 0xE48B9C + +#define mmTPC1_QM_ARB_ERR_MSG_EN 0xE48BA0 + +#define mmTPC1_QM_ARB_ERR_STS_DRP 0xE48BA8 + +#define mmTPC1_QM_ARB_MST_CRED_STS_0 0xE48BB0 + +#define mmTPC1_QM_ARB_MST_CRED_STS_1 0xE48BB4 + +#define mmTPC1_QM_ARB_MST_CRED_STS_2 0xE48BB8 + +#define mmTPC1_QM_ARB_MST_CRED_STS_3 0xE48BBC + +#define mmTPC1_QM_ARB_MST_CRED_STS_4 0xE48BC0 + +#define mmTPC1_QM_ARB_MST_CRED_STS_5 0xE48BC4 + +#define mmTPC1_QM_ARB_MST_CRED_STS_6 0xE48BC8 + +#define mmTPC1_QM_ARB_MST_CRED_STS_7 0xE48BCC + +#define mmTPC1_QM_ARB_MST_CRED_STS_8 0xE48BD0 + +#define mmTPC1_QM_ARB_MST_CRED_STS_9 0xE48BD4 + +#define mmTPC1_QM_ARB_MST_CRED_STS_10 0xE48BD8 + +#define mmTPC1_QM_ARB_MST_CRED_STS_11 0xE48BDC + +#define mmTPC1_QM_ARB_MST_CRED_STS_12 0xE48BE0 + +#define mmTPC1_QM_ARB_MST_CRED_STS_13 0xE48BE4 + +#define mmTPC1_QM_ARB_MST_CRED_STS_14 0xE48BE8 + +#define mmTPC1_QM_ARB_MST_CRED_STS_15 0xE48BEC + +#define mmTPC1_QM_ARB_MST_CRED_STS_16 0xE48BF0 + +#define mmTPC1_QM_ARB_MST_CRED_STS_17 0xE48BF4 + +#define mmTPC1_QM_ARB_MST_CRED_STS_18 0xE48BF8 + +#define mmTPC1_QM_ARB_MST_CRED_STS_19 0xE48BFC + +#define mmTPC1_QM_ARB_MST_CRED_STS_20 0xE48C00 + +#define mmTPC1_QM_ARB_MST_CRED_STS_21 0xE48C04 + +#define mmTPC1_QM_ARB_MST_CRED_STS_22 0xE48C08 + +#define mmTPC1_QM_ARB_MST_CRED_STS_23 0xE48C0C + +#define mmTPC1_QM_ARB_MST_CRED_STS_24 0xE48C10 + +#define mmTPC1_QM_ARB_MST_CRED_STS_25 0xE48C14 + +#define mmTPC1_QM_ARB_MST_CRED_STS_26 0xE48C18 + +#define mmTPC1_QM_ARB_MST_CRED_STS_27 0xE48C1C + +#define mmTPC1_QM_ARB_MST_CRED_STS_28 0xE48C20 + +#define mmTPC1_QM_ARB_MST_CRED_STS_29 0xE48C24 + +#define mmTPC1_QM_ARB_MST_CRED_STS_30 0xE48C28 + +#define mmTPC1_QM_ARB_MST_CRED_STS_31 0xE48C2C + +#define mmTPC1_QM_CGM_CFG 0xE48C70 + +#define mmTPC1_QM_CGM_STS 0xE48C74 + +#define mmTPC1_QM_CGM_CFG1 0xE48C78 + +#define mmTPC1_QM_LOCAL_RANGE_BASE 0xE48C80 + +#define mmTPC1_QM_LOCAL_RANGE_SIZE 0xE48C84 + +#define mmTPC1_QM_CSMR_STRICT_PRIO_CFG 0xE48C90 + +#define mmTPC1_QM_HBW_RD_RATE_LIM_CFG_1 0xE48C94 + +#define mmTPC1_QM_LBW_WR_RATE_LIM_CFG_0 0xE48C98 + +#define mmTPC1_QM_LBW_WR_RATE_LIM_CFG_1 0xE48C9C + +#define mmTPC1_QM_HBW_RD_RATE_LIM_CFG_0 0xE48CA0 + +#define mmTPC1_QM_GLBL_AXCACHE 0xE48CA4 + +#define mmTPC1_QM_IND_GW_APB_CFG 0xE48CB0 + +#define mmTPC1_QM_IND_GW_APB_WDATA 0xE48CB4 + +#define mmTPC1_QM_IND_GW_APB_RDATA 0xE48CB8 + +#define mmTPC1_QM_IND_GW_APB_STATUS 0xE48CBC + +#define mmTPC1_QM_GLBL_ERR_ADDR_LO 0xE48CD0 + +#define mmTPC1_QM_GLBL_ERR_ADDR_HI 0xE48CD4 + +#define mmTPC1_QM_GLBL_ERR_WDATA 0xE48CD8 + +#define mmTPC1_QM_GLBL_MEM_INIT_BUSY 0xE48D00 + +#endif /* ASIC_REG_TPC1_QM_REGS_H_ */ |