diff options
Diffstat (limited to 'drivers/staging/vt6655/rf.c')
| -rw-r--r-- | drivers/staging/vt6655/rf.c | 69 |
1 files changed, 25 insertions, 44 deletions
diff --git a/drivers/staging/vt6655/rf.c b/drivers/staging/vt6655/rf.c index edb1b2768b17..99c89a14d89b 100644 --- a/drivers/staging/vt6655/rf.c +++ b/drivers/staging/vt6655/rf.c @@ -39,8 +39,6 @@ /*--------------------- Static Definitions -------------------------*/ -//static int msglevel =MSG_LEVEL_INFO; - #define BY_AL2230_REG_LEN 23 //24bit #define CB_AL2230_INIT_SEQ 15 #define SWITCH_CHANNEL_DELAY_AL2230 200 //us @@ -183,7 +181,6 @@ static const unsigned long dwAL7230InitTable[CB_AL7230_INIT_SEQ] = { 0x841FF200+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Need modify for 11a: 451FE2 0x3FDFA300+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Need modify for 11a: 5FDFA3 0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // 11b/g // Need modify for 11a - //0x802B4500+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Need modify for 11a: 8D1B45 // RoberYu:20050113, Rev0.47 Regsiter Setting Guide 0x802B5500+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Need modify for 11a: 8D1B55 0x56AF3600+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, @@ -192,7 +189,6 @@ static const unsigned long dwAL7230InitTable[CB_AL7230_INIT_SEQ] = { 0x221BB900+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, 0xE0000A00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Need modify for 11a: E0600A 0x08031B00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // init 0x080B1B00 => 0x080F1B00 for 3 wire control TxGain(D10) - //0x00093C00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Need modify for 11a: 00143C // RoberYu:20050113, Rev0.47 Regsiter Setting Guide 0x000A3C00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Need modify for 11a: 00143C 0xFFFFFD00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, @@ -585,10 +581,9 @@ bool IFRFbWriteEmbedded(unsigned long dwIoBase, unsigned long dwData) break; } - if (ww == W_MAX_TIMEOUT) { -// DBG_PORT80_ALWAYS(0x32); + if (ww == W_MAX_TIMEOUT) return false; - } + return true; } @@ -839,13 +834,12 @@ bool RFvWriteWakeProgSyn(unsigned long dwIoBase, unsigned char byRFType, unsigne byInitCount = CB_AL2230_INIT_SEQ + 2; // Init Reg + Channel Reg (2) bySleepCount = 0; - if (byInitCount > (MISCFIFO_SYNDATASIZE - bySleepCount)) { + if (byInitCount > (MISCFIFO_SYNDATASIZE - bySleepCount)) return false; - } - for (ii = 0; ii < CB_AL2230_INIT_SEQ; ii++) { + for (ii = 0; ii < CB_AL2230_INIT_SEQ; ii++) MACvSetMISCFifo(dwIoBase, (unsigned short)(MISCFIFO_SYNDATA_IDX + ii), dwAL2230InitTable[ii]); - } + MACvSetMISCFifo(dwIoBase, (unsigned short)(MISCFIFO_SYNDATA_IDX + ii), dwAL2230ChannelTable0[uChannel-1]); ii++; MACvSetMISCFifo(dwIoBase, (unsigned short)(MISCFIFO_SYNDATA_IDX + ii), dwAL2230ChannelTable1[uChannel-1]); @@ -856,18 +850,15 @@ bool RFvWriteWakeProgSyn(unsigned long dwIoBase, unsigned char byRFType, unsigne case RF_AIROHA7230: byInitCount = CB_AL7230_INIT_SEQ + 3; // Init Reg + Channel Reg (3) bySleepCount = 0; - if (byInitCount > (MISCFIFO_SYNDATASIZE - bySleepCount)) { + if (byInitCount > (MISCFIFO_SYNDATASIZE - bySleepCount)) return false; - } if (uChannel <= CB_MAX_CHANNEL_24G) { - for (ii = 0; ii < CB_AL7230_INIT_SEQ; ii++) { + for (ii = 0; ii < CB_AL7230_INIT_SEQ; ii++) MACvSetMISCFifo(dwIoBase, (unsigned short)(MISCFIFO_SYNDATA_IDX + ii), dwAL7230InitTable[ii]); - } } else { - for (ii = 0; ii < CB_AL7230_INIT_SEQ; ii++) { + for (ii = 0; ii < CB_AL7230_INIT_SEQ; ii++) MACvSetMISCFifo(dwIoBase, (unsigned short)(MISCFIFO_SYNDATA_IDX + ii), dwAL7230InitTableAMode[ii]); - } } MACvSetMISCFifo(dwIoBase, (unsigned short)(MISCFIFO_SYNDATA_IDX + ii), dwAL7230ChannelTable0[uChannel-1]); @@ -916,12 +907,11 @@ bool RFbSetPower( unsigned char byDec = 0; unsigned char byPwrdBm = 0; - if (pDevice->dwDiagRefCount != 0) { + if (pDevice->dwDiagRefCount != 0) return true; - } - if ((uCH < 1) || (uCH > CB_MAX_CHANNEL)) { + + if ((uCH < 1) || (uCH > CB_MAX_CHANNEL)) return false; - } switch (uRATE) { case RATE_1M: @@ -930,22 +920,19 @@ bool RFbSetPower( case RATE_11M: byPwr = pDevice->abyCCKPwrTbl[uCH]; byPwrdBm = pDevice->abyCCKDefaultPwr[uCH]; -//PLICE_DEBUG-> - //byPwr+=5; -//PLICE_DEBUG <- break; case RATE_6M: case RATE_9M: case RATE_18M: byPwr = pDevice->abyOFDMPwrTbl[uCH]; - if (pDevice->byRFType == RF_UW2452) { + if (pDevice->byRFType == RF_UW2452) byDec = byPwr + 14; - } else { + else byDec = byPwr + 10; - } - if (byDec >= pDevice->byMaxPwrLevel) { + + if (byDec >= pDevice->byMaxPwrLevel) byDec = pDevice->byMaxPwrLevel-1; - } + if (pDevice->byRFType == RF_UW2452) { byPwrdBm = byDec - byPwr; byPwrdBm /= 3; @@ -953,11 +940,9 @@ bool RFbSetPower( byPwrdBm = byDec - byPwr; byPwrdBm >>= 1; } + byPwrdBm += pDevice->abyOFDMDefaultPwr[uCH]; byPwr = byDec; -//PLICE_DEBUG-> - //byPwr+=5; -//PLICE_DEBUG<- break; case RATE_24M: case RATE_36M: @@ -965,20 +950,16 @@ bool RFbSetPower( case RATE_54M: byPwr = pDevice->abyOFDMPwrTbl[uCH]; byPwrdBm = pDevice->abyOFDMDefaultPwr[uCH]; -//PLICE_DEBUG-> - //byPwr+=5; -//PLICE_DEBUG<- break; } - if (pDevice->byCurPwr == byPwr) { + if (pDevice->byCurPwr == byPwr) return true; - } bResult = RFbRawSetPower(pDevice, byPwr, uRATE); - if (bResult) { + if (bResult) pDevice->byCurPwr = byPwr; - } + return bResult; } @@ -1005,17 +986,17 @@ bool RFbRawSetPower( bool bResult = true; unsigned long dwMax7230Pwr = 0; - if (byPwr >= pDevice->byMaxPwrLevel) { + if (byPwr >= pDevice->byMaxPwrLevel) return false; - } + switch (pDevice->byRFType) { case RF_AIROHA: bResult &= IFRFbWriteEmbedded(pDevice->PortOffset, dwAL2230PowerTable[byPwr]); - if (uRATE <= RATE_11M) { + if (uRATE <= RATE_11M) bResult &= IFRFbWriteEmbedded(pDevice->PortOffset, 0x0001B400+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW); - } else { + else bResult &= IFRFbWriteEmbedded(pDevice->PortOffset, 0x0005A400+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW); - } + break; case RF_AL2230S: |