diff options
Diffstat (limited to '')
| -rw-r--r-- | tools/perf/pmu-events/arch/x86/haswell/pipeline.json | 1747 |
1 files changed, 727 insertions, 1020 deletions
diff --git a/tools/perf/pmu-events/arch/x86/haswell/pipeline.json b/tools/perf/pmu-events/arch/x86/haswell/pipeline.json index 734d3873729e..540f4372623c 100644 --- a/tools/perf/pmu-events/arch/x86/haswell/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/haswell/pipeline.json @@ -1,1343 +1,1050 @@ [ { - "PublicDescription": "This event counts the number of instructions retired from execution. For instructions that consist of multiple micro-ops, this event counts the retirement of the last micro-op of the instruction. Counting continues during hardware interrupts, traps, and inside interrupt handlers. INST_RETIRED.ANY is counted by a designated fixed counter, leaving the programmable counters available for other events. Faulting executions of GETSEC/VM entry/VM Exit/MWait will not count as retired instructions.", - "Counter": "Fixed counter 0", - "UMask": "0x1", - "Errata": "HSD140, HSD143", - "EventName": "INST_RETIRED.ANY", - "SampleAfterValue": "2000003", - "BriefDescription": "Instructions retired from execution.", - "CounterHTOff": "Fixed counter 0" - }, - { - "PublicDescription": "This event counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling.", - "Counter": "Fixed counter 1", - "UMask": "0x2", - "EventName": "CPU_CLK_UNHALTED.THREAD", - "SampleAfterValue": "2000003", - "BriefDescription": "Core cycles when the thread is not in halt state.", - "CounterHTOff": "Fixed counter 1" - }, - { - "Counter": "Fixed counter 1", - "UMask": "0x2", - "AnyThread": "1", - "EventName": "CPU_CLK_UNHALTED.THREAD_ANY", - "SampleAfterValue": "2000003", - "BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state.", - "CounterHTOff": "Fixed counter 1" - }, - { - "PublicDescription": "This event counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state.", - "Counter": "Fixed counter 2", - "UMask": "0x3", - "EventName": "CPU_CLK_UNHALTED.REF_TSC", - "SampleAfterValue": "2000003", - "BriefDescription": "Reference cycles when the core is not in halt state.", - "CounterHTOff": "Fixed counter 2" - }, - { - "PublicDescription": "This event counts loads that followed a store to the same address, where the data could not be forwarded inside the pipeline from the store to the load. The most common reason why store forwarding would be blocked is when a load's address range overlaps with a preceding smaller uncompleted store. The penalty for blocked store forwarding is that the load must wait for the store to write its value to the cache before it can be issued.", - "EventCode": "0x03", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "LD_BLOCKS.STORE_FORWARD", - "SampleAfterValue": "100003", - "BriefDescription": "loads blocked by overlapping with store buffer that cannot be forwarded", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "The number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.", - "EventCode": "0x03", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "LD_BLOCKS.NO_SR", - "SampleAfterValue": "100003", - "BriefDescription": "The number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Aliasing occurs when a load is issued after a store and their memory addresses are offset by 4K. This event counts the number of loads that aliased with a preceding store, resulting in an extended address check in the pipeline which can have a performance impact.", - "EventCode": "0x07", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS", - "SampleAfterValue": "100003", - "BriefDescription": "False dependencies in MOB due to partial compare on address.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event counts the number of cycles spent waiting for a recovery after an event such as a processor nuke, JEClear, assist, hle/rtm abort etc.", - "EventCode": "0x0D", - "Counter": "0,1,2,3", - "UMask": "0x3", - "EventName": "INT_MISC.RECOVERY_CYCLES", + "BriefDescription": "Any uop executed by the Divider. (This includes all divide uops, sqrt, ...)", + "EventCode": "0x14", + "EventName": "ARITH.DIVIDER_UOPS", "SampleAfterValue": "2000003", - "BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for this thread (e.g. misprediction or memory nuke)", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "PublicDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke).", - "EventCode": "0x0D", - "Counter": "0,1,2,3", - "UMask": "0x3", - "AnyThread": "1", - "EventName": "INT_MISC.RECOVERY_CYCLES_ANY", - "SampleAfterValue": "2000003", - "BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke)", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "BriefDescription": "Speculative and retired branches", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.ALL_BRANCHES", + "PublicDescription": "Counts all near executed branches (not necessarily retired).", + "SampleAfterValue": "200003", + "UMask": "0xff" }, { - "PublicDescription": "This event counts the number of uops issued by the Front-end of the pipeline to the Back-end. This event is counted at the allocation stage and will count both retired and non-retired uops.", - "EventCode": "0x0E", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_ISSUED.ANY", - "SampleAfterValue": "2000003", - "BriefDescription": "Uops that Resource Allocation Table (RAT) issues to Reservation Station (RS)", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "BriefDescription": "Speculative and retired macro-conditional branches.", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.ALL_CONDITIONAL", + "SampleAfterValue": "200003", + "UMask": "0xc1" }, { - "EventCode": "0x0E", - "Invert": "1", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_ISSUED.STALL_CYCLES", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3" + "BriefDescription": "Speculative and retired macro-unconditional branches excluding calls and indirects.", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.ALL_DIRECT_JMP", + "SampleAfterValue": "200003", + "UMask": "0xc2" }, { - "EventCode": "0x0E", - "Invert": "1", - "Counter": "0,1,2,3", - "UMask": "0x1", - "AnyThread": "1", - "EventName": "UOPS_ISSUED.CORE_STALL_CYCLES", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for all threads.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3" + "BriefDescription": "Speculative and retired direct near calls.", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.ALL_DIRECT_NEAR_CALL", + "SampleAfterValue": "200003", + "UMask": "0xd0" }, { - "PublicDescription": "Number of flags-merge uops allocated. Such uops add delay.", - "EventCode": "0x0E", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "UOPS_ISSUED.FLAGS_MERGE", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of flags-merge uops being allocated. Such uops considered perf sensitive; added by GSR u-arch.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "BriefDescription": "Speculative and retired indirect branches excluding calls and returns.", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET", + "SampleAfterValue": "200003", + "UMask": "0xc4" }, { - "PublicDescription": "Number of slow LEA or similar uops allocated. Such uop has 3 sources (for example, 2 sources + immediate) regardless of whether it is a result of LEA instruction or not.", - "EventCode": "0x0E", - "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "UOPS_ISSUED.SLOW_LEA", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of slow LEA uops being allocated. A uop is generally considered SlowLea if it has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "BriefDescription": "Speculative and retired indirect return branches.", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.ALL_INDIRECT_NEAR_RETURN", + "SampleAfterValue": "200003", + "UMask": "0xc8" }, { - "PublicDescription": "Number of multiply packed/scalar single precision uops allocated.", - "EventCode": "0x0E", - "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "UOPS_ISSUED.SINGLE_MUL", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of Multiply packed/scalar single precision uops allocated", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "BriefDescription": "Not taken macro-conditional branches.", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.NONTAKEN_CONDITIONAL", + "SampleAfterValue": "200003", + "UMask": "0x41" }, { - "EventCode": "0x14", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "ARITH.DIVIDER_UOPS", - "SampleAfterValue": "2000003", - "BriefDescription": "Any uop executed by the Divider. (This includes all divide uops, sqrt, ...)", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "BriefDescription": "Taken speculative and retired macro-conditional branches.", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.TAKEN_CONDITIONAL", + "SampleAfterValue": "200003", + "UMask": "0x81" }, { - "PublicDescription": "Counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling.", - "EventCode": "0x3C", - "Counter": "0,1,2,3", - "UMask": "0x0", - "EventName": "CPU_CLK_UNHALTED.THREAD_P", - "SampleAfterValue": "2000003", - "BriefDescription": "Thread cycles when thread is not in halt state", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "BriefDescription": "Taken speculative and retired macro-conditional branch instructions excluding calls and indirects.", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.TAKEN_DIRECT_JUMP", + "SampleAfterValue": "200003", + "UMask": "0x82" }, { - "EventCode": "0x3C", - "Counter": "0,1,2,3", - "UMask": "0x0", - "AnyThread": "1", - "EventName": "CPU_CLK_UNHALTED.THREAD_P_ANY", - "SampleAfterValue": "2000003", - "BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "BriefDescription": "Taken speculative and retired direct near calls.", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.TAKEN_DIRECT_NEAR_CALL", + "SampleAfterValue": "200003", + "UMask": "0x90" }, { - "PublicDescription": "Increments at the frequency of XCLK (100 MHz) when not halted.", - "EventCode": "0x3C", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK", - "SampleAfterValue": "2000003", - "BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "BriefDescription": "Taken speculative and retired indirect branches excluding calls and returns.", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET", + "SampleAfterValue": "200003", + "UMask": "0x84" }, { - "PublicDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate).", - "EventCode": "0x3C", - "Counter": "0,1,2,3", - "UMask": "0x1", - "AnyThread": "1", - "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY", - "SampleAfterValue": "2000003", - "BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate)", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "BriefDescription": "Taken speculative and retired indirect calls.", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_CALL", + "SampleAfterValue": "200003", + "UMask": "0xa0" }, { - "PublicDescription": "Reference cycles when the thread is unhalted. (counts at 100 MHz rate)", - "EventCode": "0x3C", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "CPU_CLK_UNHALTED.REF_XCLK", - "SampleAfterValue": "2000003", - "BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "BriefDescription": "Taken speculative and retired indirect branches with return mnemonic.", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_RETURN", + "SampleAfterValue": "200003", + "UMask": "0x88" }, { - "PublicDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate).", - "EventCode": "0x3C", - "Counter": "0,1,2,3", - "UMask": "0x1", - "AnyThread": "1", - "EventName": "CPU_CLK_UNHALTED.REF_XCLK_ANY", - "SampleAfterValue": "2000003", - "BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate)", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "BriefDescription": "All (macro) branch instructions retired.", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.ALL_BRANCHES", + "PublicDescription": "Branch instructions at retirement.", + "SampleAfterValue": "400009" }, { - "EventCode": "0x3c", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE", - "SampleAfterValue": "2000003", - "BriefDescription": "Count XClk pulses when this thread is unhalted and the other thread is halted.", - "CounterHTOff": "0,1,2,3" + "BriefDescription": "All (macro) branch instructions retired.", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.ALL_BRANCHES_PEBS", + "PEBS": "2", + "SampleAfterValue": "400009", + "UMask": "0x4" }, { - "EventCode": "0x3C", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE", - "SampleAfterValue": "2000003", - "BriefDescription": "Count XClk pulses when this thread is unhalted and the other thread is halted.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "BriefDescription": "Conditional branch instructions retired.", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.CONDITIONAL", + "PEBS": "1", + "PublicDescription": "Counts the number of conditional branch instructions retired.", + "SampleAfterValue": "400009", + "UMask": "0x1" }, { - "PublicDescription": "Non-SW-prefetch load dispatches that hit fill buffer allocated for S/W prefetch.", - "EventCode": "0x4c", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "LOAD_HIT_PRE.SW_PF", + "BriefDescription": "Far branch instructions retired.", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.FAR_BRANCH", + "PublicDescription": "Number of far branches retired.", "SampleAfterValue": "100003", - "BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for software prefetch", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x40" }, { - "PublicDescription": "Non-SW-prefetch load dispatches that hit fill buffer allocated for H/W prefetch.", - "EventCode": "0x4c", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "LOAD_HIT_PRE.HW_PF", + "BriefDescription": "Direct and indirect near call instructions retired.", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.NEAR_CALL", + "PEBS": "1", "SampleAfterValue": "100003", - "BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for hardware prefetch", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "PublicDescription": "Number of integer move elimination candidate uops that were eliminated.", - "EventCode": "0x58", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "MOVE_ELIMINATION.INT_ELIMINATED", - "SampleAfterValue": "1000003", - "BriefDescription": "Number of integer Move Elimination candidate uops that were eliminated.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Number of SIMD move elimination candidate uops that were eliminated.", - "EventCode": "0x58", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "MOVE_ELIMINATION.SIMD_ELIMINATED", - "SampleAfterValue": "1000003", - "BriefDescription": "Number of SIMD Move Elimination candidate uops that were eliminated.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "BriefDescription": "Direct and indirect macro near call instructions retired (captured in ring 3).", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.NEAR_CALL_R3", + "PEBS": "1", + "SampleAfterValue": "100003", + "UMask": "0x2" }, { - "PublicDescription": "Number of integer move elimination candidate uops that were not eliminated.", - "EventCode": "0x58", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "MOVE_ELIMINATION.INT_NOT_ELIMINATED", - "SampleAfterValue": "1000003", - "BriefDescription": "Number of integer Move Elimination candidate uops that were not eliminated.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "BriefDescription": "Return instructions retired.", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.NEAR_RETURN", + "PEBS": "1", + "PublicDescription": "Counts the number of near return instructions retired.", + "SampleAfterValue": "100003", + "UMask": "0x8" }, { - "PublicDescription": "Number of SIMD move elimination candidate uops that were not eliminated.", - "EventCode": "0x58", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "MOVE_ELIMINATION.SIMD_NOT_ELIMINATED", - "SampleAfterValue": "1000003", - "BriefDescription": "Number of SIMD Move Elimination candidate uops that were not eliminated.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "BriefDescription": "Taken branch instructions retired.", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.NEAR_TAKEN", + "PEBS": "1", + "PublicDescription": "Number of near taken branches retired.", + "SampleAfterValue": "400009", + "UMask": "0x20" }, { - "PublicDescription": "This event counts cycles when the Reservation Station ( RS ) is empty for the thread. The RS is a structure that buffers allocated micro-ops from the Front-end. If there are many cycles when the RS is empty, it may represent an underflow of instructions delivered from the Front-end.", - "EventCode": "0x5E", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "RS_EVENTS.EMPTY_CYCLES", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when Reservation Station (RS) is empty for the thread", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "BriefDescription": "Not taken branch instructions retired.", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.NOT_TAKEN", + "PublicDescription": "Counts the number of not taken branch instructions retired.", + "SampleAfterValue": "400009", + "UMask": "0x10" }, { - "EventCode": "0x5E", - "Invert": "1", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EdgeDetect": "1", - "EventName": "RS_EVENTS.EMPTY_END", + "BriefDescription": "Speculative and retired mispredicted macro conditional branches", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.ALL_BRANCHES", + "PublicDescription": "Counts all near executed branches (not necessarily retired).", "SampleAfterValue": "200003", - "BriefDescription": "Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound issues.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0xff" }, { - "PublicDescription": "This event counts cycles where the decoder is stalled on an instruction with a length changing prefix (LCP).", - "EventCode": "0x87", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "ILD_STALL.LCP", - "SampleAfterValue": "2000003", - "BriefDescription": "Stalls caused by changing prefix length of the instruction.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "BriefDescription": "Speculative and retired mispredicted macro conditional branches.", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.ALL_CONDITIONAL", + "SampleAfterValue": "200003", + "UMask": "0xc1" }, { - "PublicDescription": "Stall cycles due to IQ is full.", - "EventCode": "0x87", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "ILD_STALL.IQ_FULL", - "SampleAfterValue": "2000003", - "BriefDescription": "Stall cycles because IQ is full", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "BriefDescription": "Mispredicted indirect branches excluding calls and returns.", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET", + "SampleAfterValue": "200003", + "UMask": "0xc4" }, { - "EventCode": "0x88", - "Counter": "0,1,2,3", - "UMask": "0x41", - "EventName": "BR_INST_EXEC.NONTAKEN_CONDITIONAL", + "BriefDescription": "Speculative mispredicted indirect branches", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.INDIRECT", + "PublicDescription": "Counts speculatively miss-predicted indirect branches at execution time. Counts for indirect near CALL or JMP instructions (RET excluded).", "SampleAfterValue": "200003", - "BriefDescription": "Not taken macro-conditional branches.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0xe4" }, { - "EventCode": "0x88", - "Counter": "0,1,2,3", - "UMask": "0x81", - "EventName": "BR_INST_EXEC.TAKEN_CONDITIONAL", + "BriefDescription": "Not taken speculative and retired mispredicted macro conditional branches.", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.NONTAKEN_CONDITIONAL", "SampleAfterValue": "200003", - "BriefDescription": "Taken speculative and retired macro-conditional branches.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x41" }, { - "EventCode": "0x88", - "Counter": "0,1,2,3", - "UMask": "0x82", - "EventName": "BR_INST_EXEC.TAKEN_DIRECT_JUMP", + "BriefDescription": "Taken speculative and retired mispredicted macro conditional branches.", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.TAKEN_CONDITIONAL", "SampleAfterValue": "200003", - "BriefDescription": "Taken speculative and retired macro-conditional branch instructions excluding calls and indirects.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x81" }, { - "EventCode": "0x88", - "Counter": "0,1,2,3", - "UMask": "0x84", - "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET", + "BriefDescription": "Taken speculative and retired mispredicted indirect branches excluding calls and returns.", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET", "SampleAfterValue": "200003", - "BriefDescription": "Taken speculative and retired indirect branches excluding calls and returns.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x84" }, { - "EventCode": "0x88", - "Counter": "0,1,2,3", - "UMask": "0x88", - "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_RETURN", + "BriefDescription": "Taken speculative and retired mispredicted indirect calls.", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_NEAR_CALL", "SampleAfterValue": "200003", - "BriefDescription": "Taken speculative and retired indirect branches with return mnemonic.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0xa0" }, { - "EventCode": "0x88", - "Counter": "0,1,2,3", - "UMask": "0x90", - "EventName": "BR_INST_EXEC.TAKEN_DIRECT_NEAR_CALL", + "BriefDescription": "Taken speculative and retired mispredicted indirect branches with return mnemonic.", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.TAKEN_RETURN_NEAR", "SampleAfterValue": "200003", - "BriefDescription": "Taken speculative and retired direct near calls.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x88" }, { - "EventCode": "0x88", - "Counter": "0,1,2,3", - "UMask": "0xa0", - "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_CALL", - "SampleAfterValue": "200003", - "BriefDescription": "Taken speculative and retired indirect calls.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "BriefDescription": "All mispredicted macro branch instructions retired.", + "EventCode": "0xC5", + "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", + "PublicDescription": "Mispredicted branch instructions at retirement.", + "SampleAfterValue": "400009" }, { - "EventCode": "0x88", - "Counter": "0,1,2,3", - "UMask": "0xc1", - "EventName": "BR_INST_EXEC.ALL_CONDITIONAL", - "SampleAfterValue": "200003", - "BriefDescription": "Speculative and retired macro-conditional branches.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "BriefDescription": "Mispredicted macro branch instructions retired.", + "EventCode": "0xC5", + "EventName": "BR_MISP_RETIRED.ALL_BRANCHES_PEBS", + "PEBS": "2", + "PublicDescription": "This event counts all mispredicted branch instructions retired. This is a precise event.", + "SampleAfterValue": "400009", + "UMask": "0x4" }, { - "EventCode": "0x88", - "Counter": "0,1,2,3", - "UMask": "0xc2", - "EventName": "BR_INST_EXEC.ALL_DIRECT_JMP", - "SampleAfterValue": "200003", - "BriefDescription": "Speculative and retired macro-unconditional branches excluding calls and indirects.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "BriefDescription": "Mispredicted conditional branch instructions retired.", + "EventCode": "0xC5", + "EventName": "BR_MISP_RETIRED.CONDITIONAL", + "PEBS": "1", + "SampleAfterValue": "400009", + "UMask": "0x1" }, { - "EventCode": "0x88", - "Counter": "0,1,2,3", - "UMask": "0xc4", - "EventName": "BR_INST_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET", - "SampleAfterValue": "200003", - "BriefDescription": "Speculative and retired indirect branches excluding calls and returns.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "BriefDescription": "number of near branch instructions retired that were mispredicted and taken.", + "EventCode": "0xC5", + "EventName": "BR_MISP_RETIRED.NEAR_TAKEN", + "PEBS": "1", + "PublicDescription": "Number of near branch instructions retired that were taken but mispredicted.", + "SampleAfterValue": "400009", + "UMask": "0x20" }, { - "EventCode": "0x88", - "Counter": "0,1,2,3", - "UMask": "0xc8", - "EventName": "BR_INST_EXEC.ALL_INDIRECT_NEAR_RETURN", - "SampleAfterValue": "200003", - "BriefDescription": "Speculative and retired indirect return branches.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "BriefDescription": "Count XClk pulses when this thread is unhalted and the other thread is halted.", + "EventCode": "0x3c", + "EventName": "CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE", + "SampleAfterValue": "100003", + "UMask": "0x2" }, { - "EventCode": "0x88", - "Counter": "0,1,2,3", - "UMask": "0xd0", - "EventName": "BR_INST_EXEC.ALL_DIRECT_NEAR_CALL", - "SampleAfterValue": "200003", - "BriefDescription": "Speculative and retired direct near calls.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)", + "EventCode": "0x3C", + "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK", + "PublicDescription": "Increments at the frequency of XCLK (100 MHz) when not halted.", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts all near executed branches (not necessarily retired).", - "EventCode": "0x88", - "Counter": "0,1,2,3", - "UMask": "0xff", - "EventName": "BR_INST_EXEC.ALL_BRANCHES", - "SampleAfterValue": "200003", - "BriefDescription": "Speculative and retired branches", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "AnyThread": "1", + "BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate)", + "EventCode": "0x3C", + "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY", + "PublicDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate).", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "EventCode": "0x89", - "Counter": "0,1,2,3", - "UMask": "0x41", - "EventName": "BR_MISP_EXEC.NONTAKEN_CONDITIONAL", - "SampleAfterValue": "200003", - "BriefDescription": "Not taken speculative and retired mispredicted macro conditional branches.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "BriefDescription": "Count XClk pulses when this thread is unhalted and the other thread is halted.", + "EventCode": "0x3C", + "EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE", + "SampleAfterValue": "100003", + "UMask": "0x2" }, { - "EventCode": "0x89", - "Counter": "0,1,2,3", - "UMask": "0x81", - "EventName": "BR_MISP_EXEC.TAKEN_CONDITIONAL", - "SampleAfterValue": "200003", - "BriefDescription": "Taken speculative and retired mispredicted macro conditional branches.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "BriefDescription": "Reference cycles when the core is not in halt state.", + "EventName": "CPU_CLK_UNHALTED.REF_TSC", + "PublicDescription": "This event counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state.", + "SampleAfterValue": "2000003", + "UMask": "0x3" }, { - "EventCode": "0x89", - "Counter": "0,1,2,3", - "UMask": "0x84", - "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET", - "SampleAfterValue": "200003", - "BriefDescription": "Taken speculative and retired mispredicted indirect branches excluding calls and returns.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)", + "EventCode": "0x3C", + "EventName": "CPU_CLK_UNHALTED.REF_XCLK", + "PublicDescription": "Reference cycles when the thread is unhalted. (counts at 100 MHz rate)", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "EventCode": "0x89", - "Counter": "0,1,2,3", - "UMask": "0x88", - "EventName": "BR_MISP_EXEC.TAKEN_RETURN_NEAR", - "SampleAfterValue": "200003", - "BriefDescription": "Taken speculative and retired mispredicted indirect branches with return mnemonic.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "AnyThread": "1", + "BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate)", + "EventCode": "0x3C", + "EventName": "CPU_CLK_UNHALTED.REF_XCLK_ANY", + "PublicDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate).", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "EventCode": "0x89", - "Counter": "0,1,2,3", - "UMask": "0xa0", - "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_NEAR_CALL", - "SampleAfterValue": "200003", - "BriefDescription": "Taken speculative and retired mispredicted indirect calls.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "BriefDescription": "Core cycles when the thread is not in halt state.", + "EventName": "CPU_CLK_UNHALTED.THREAD", + "PublicDescription": "This event counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling.", + "SampleAfterValue": "2000003", + "UMask": "0x2" }, { - "EventCode": "0x89", - "Counter": "0,1,2,3", - "UMask": "0xc1", - "EventName": "BR_MISP_EXEC.ALL_CONDITIONAL", - "SampleAfterValue": "200003", - "BriefDescription": "Speculative and retired mispredicted macro conditional branches.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "AnyThread": "1", + "BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state.", + "EventName": "CPU_CLK_UNHALTED.THREAD_ANY", + "SampleAfterValue": "2000003", + "UMask": "0x2" }, { - "EventCode": "0x89", - "Counter": "0,1,2,3", - "UMask": "0xc4", - "EventName": "BR_MISP_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET", - "SampleAfterValue": "200003", - "BriefDescription": "Mispredicted indirect branches excluding calls and returns.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "BriefDescription": "Thread cycles when thread is not in halt state", + "EventCode": "0x3C", + "EventName": "CPU_CLK_UNHALTED.THREAD_P", + "PublicDescription": "Counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling.", + "SampleAfterValue": "2000003" }, { - "PublicDescription": "Counts all near executed branches (not necessarily retired).", - "EventCode": "0x89", - "Counter": "0,1,2,3", - "UMask": "0xff", - "EventName": "BR_MISP_EXEC.ALL_BRANCHES", - "SampleAfterValue": "200003", - "BriefDescription": "Speculative and retired mispredicted macro conditional branches", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "AnyThread": "1", + "BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state.", + "EventCode": "0x3C", + "EventName": "CPU_CLK_UNHALTED.THREAD_P_ANY", + "SampleAfterValue": "2000003" }, { - "PublicDescription": "Cycles which a uop is dispatched on port 0 in this thread.", - "EventCode": "0xA1", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_EXECUTED_PORT.PORT_0", + "BriefDescription": "Cycles with pending L1 cache miss loads.", + "CounterMask": "8", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_PENDING", + "PublicDescription": "Cycles with pending L1 data cache miss loads. Set Cmask=8 to count cycle.", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per thread when uops are executed in port 0", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x8" }, { - "PublicDescription": "Cycles per core when uops are exectuted in port 0.", - "EventCode": "0xA1", - "Counter": "0,1,2,3", - "UMask": "0x1", - "AnyThread": "1", - "EventName": "UOPS_EXECUTED_PORT.PORT_0_CORE", + "BriefDescription": "Cycles with pending L2 cache miss loads.", + "CounterMask": "1", + "Errata": "HSD78, HSM63, HSM80", + "EventCode": "0xa3", + "EventName": "CYCLE_ACTIVITY.CYCLES_L2_PENDING", + "PublicDescription": "Cycles with pending L2 miss loads. Set Cmask=2 to count cycle.", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per core when uops are executed in port 0.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0xA1", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_DISPATCHED_PORT.PORT_0", + "BriefDescription": "Cycles with pending memory loads.", + "CounterMask": "2", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.CYCLES_LDM_PENDING", + "PublicDescription": "Cycles with pending memory loads. Set Cmask=2 to count cycle.", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per thread when uops are executed in port 0.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "PublicDescription": "Cycles which a uop is dispatched on port 1 in this thread.", - "EventCode": "0xA1", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "UOPS_EXECUTED_PORT.PORT_1", + "BriefDescription": "This event increments by 1 for every cycle where there was no execute for this thread.", + "CounterMask": "4", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.CYCLES_NO_EXECUTE", + "PublicDescription": "This event counts cycles during which no instructions were executed in the execution stage of the pipeline.", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per thread when uops are executed in port 1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x4" }, { - "PublicDescription": "Cycles per core when uops are exectuted in port 1.", - "EventCode": "0xA1", - "Counter": "0,1,2,3", - "UMask": "0x2", - "AnyThread": "1", - "EventName": "UOPS_EXECUTED_PORT.PORT_1_CORE", + "BriefDescription": "Execution stalls due to L1 data cache misses", + "CounterMask": "12", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.STALLS_L1D_PENDING", + "PublicDescription": "Execution stalls due to L1 data cache miss loads. Set Cmask=0CH.", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per core when uops are executed in port 1.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0xc" }, { - "EventCode": "0xA1", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "UOPS_DISPATCHED_PORT.PORT_1", + "BriefDescription": "Execution stalls due to L2 cache misses.", + "CounterMask": "5", + "Errata": "HSM63, HSM80", + "EventCode": "0xa3", + "EventName": "CYCLE_ACTIVITY.STALLS_L2_PENDING", + "PublicDescription": "Number of loads missed L2.", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per thread when uops are executed in port 1.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x5" }, { - "PublicDescription": "Cycles which a uop is dispatched on port 2 in this thread.", - "EventCode": "0xA1", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "UOPS_EXECUTED_PORT.PORT_2", + "BriefDescription": "Execution stalls due to memory subsystem.", + "CounterMask": "6", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.STALLS_LDM_PENDING", + "PublicDescription": "This event counts cycles during which no instructions were executed in the execution stage of the pipeline and there were memory instructions pending (waiting for data).", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per thread when uops are executed in port 2", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x6" }, { - "EventCode": "0xA1", - "Counter": "0,1,2,3", - "UMask": "0x4", - "AnyThread": "1", - "EventName": "UOPS_EXECUTED_PORT.PORT_2_CORE", + "BriefDescription": "Stall cycles because IQ is full", + "EventCode": "0x87", + "EventName": "ILD_STALL.IQ_FULL", + "PublicDescription": "Stall cycles due to IQ is full.", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per core when uops are dispatched to port 2.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x4" }, { - "EventCode": "0xA1", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "UOPS_DISPATCHED_PORT.PORT_2", + "BriefDescription": "Stalls caused by changing prefix length of the instruction.", + "EventCode": "0x87", + "EventName": "ILD_STALL.LCP", + "PublicDescription": "This event counts cycles where the decoder is stalled on an instruction with a length changing prefix (LCP).", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per thread when uops are executed in port 2.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "PublicDescription": "Cycles which a uop is dispatched on port 3 in this thread.", - "EventCode": "0xA1", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "UOPS_EXECUTED_PORT.PORT_3", + "BriefDescription": "Instructions retired from execution.", + "Errata": "HSD140, HSD143", + "EventName": "INST_RETIRED.ANY", + "PublicDescription": "This event counts the number of instructions retired from execution. For instructions that consist of multiple micro-ops, this event counts the retirement of the last micro-op of the instruction. Counting continues during hardware interrupts, traps, and inside interrupt handlers. INST_RETIRED.ANY is counted by a designated fixed counter, leaving the programmable counters available for other events. Faulting executions of GETSEC/VM entry/VM Exit/MWait will not count as retired instructions.", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per thread when uops are executed in port 3", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0xA1", - "Counter": "0,1,2,3", - "UMask": "0x8", - "AnyThread": "1", - "EventName": "UOPS_EXECUTED_PORT.PORT_3_CORE", + "BriefDescription": "Number of instructions retired. General Counter - architectural event", + "Errata": "HSD11, HSD140", + "EventCode": "0xC0", + "EventName": "INST_RETIRED.ANY_P", + "PublicDescription": "Number of instructions at retirement.", + "SampleAfterValue": "2000003" + }, + { + "BriefDescription": "Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution", + "Errata": "HSD140", + "EventCode": "0xC0", + "EventName": "INST_RETIRED.PREC_DIST", + "PEBS": "2", + "PublicDescription": "Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution.", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per core when uops are dispatched to port 3.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0xA1", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "UOPS_DISPATCHED_PORT.PORT_3", + "BriefDescription": "FP operations retired. X87 FP operations that have no exceptions: Counts also flows that have several X87 or flows that use X87 uops in the exception handling.", + "EventCode": "0xC0", + "EventName": "INST_RETIRED.X87", + "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts FP operations retired. For X87 FP operations that have no exceptions counting also includes flows that have several X87, or flows that use X87 uops in the exception handling.", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per thread when uops are executed in port 3.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "PublicDescription": "Cycles which a uop is dispatched on port 4 in this thread.", - "EventCode": "0xA1", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "UOPS_EXECUTED_PORT.PORT_4", + "BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for this thread (e.g. misprediction or memory nuke)", + "CounterMask": "1", + "EventCode": "0x0D", + "EventName": "INT_MISC.RECOVERY_CYCLES", + "PublicDescription": "This event counts the number of cycles spent waiting for a recovery after an event such as a processor nuke, JEClear, assist, hle/rtm abort etc.", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per thread when uops are executed in port 4", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x3" }, { - "PublicDescription": "Cycles per core when uops are exectuted in port 4.", - "EventCode": "0xA1", - "Counter": "0,1,2,3", - "UMask": "0x10", "AnyThread": "1", - "EventName": "UOPS_EXECUTED_PORT.PORT_4_CORE", + "BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke)", + "CounterMask": "1", + "EventCode": "0x0D", + "EventName": "INT_MISC.RECOVERY_CYCLES_ANY", + "PublicDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke).", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per core when uops are executed in port 4.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x3" }, { - "EventCode": "0xA1", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "UOPS_DISPATCHED_PORT.PORT_4", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per thread when uops are executed in port 4.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "BriefDescription": "The number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use", + "EventCode": "0x03", + "EventName": "LD_BLOCKS.NO_SR", + "PublicDescription": "The number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.", + "SampleAfterValue": "100003", + "UMask": "0x8" }, { - "PublicDescription": "Cycles which a uop is dispatched on port 5 in this thread.", - "EventCode": "0xA1", - "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "UOPS_EXECUTED_PORT.PORT_5", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per thread when uops are executed in port 5", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "BriefDescription": "loads blocked by overlapping with store buffer that cannot be forwarded", + "EventCode": "0x03", + "EventName": "LD_BLOCKS.STORE_FORWARD", + "PublicDescription": "This event counts loads that followed a store to the same address, where the data could not be forwarded inside the pipeline from the store to the load. The most common reason why store forwarding would be blocked is when a load's address range overlaps with a preceding smaller uncompleted store. The penalty for blocked store forwarding is that the load must wait for the store to write its value to the cache before it can be issued.", + "SampleAfterValue": "100003", + "UMask": "0x2" }, { - "PublicDescription": "Cycles per core when uops are exectuted in port 5.", - "EventCode": "0xA1", - "Counter": "0,1,2,3", - "UMask": "0x20", - "AnyThread": "1", - "EventName": "UOPS_EXECUTED_PORT.PORT_5_CORE", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per core when uops are executed in port 5.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "BriefDescription": "False dependencies in MOB due to partial compare on address.", + "EventCode": "0x07", + "EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS", + "PublicDescription": "Aliasing occurs when a load is issued after a store and their memory addresses are offset by 4K. This event counts the number of loads that aliased with a preceding store, resulting in an extended address check in the pipeline which can have a performance impact.", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "EventCode": "0xA1", - "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "UOPS_DISPATCHED_PORT.PORT_5", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per thread when uops are executed in port 5.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for hardware prefetch", + "EventCode": "0x4c", + "EventName": "LOAD_HIT_PRE.HW_PF", + "PublicDescription": "Non-SW-prefetch load dispatches that hit fill buffer allocated for H/W prefetch.", + "SampleAfterValue": "100003", + "UMask": "0x2" }, { - "PublicDescription": "Cycles which a uop is dispatched on port 6 in this thread.", - "EventCode": "0xA1", - "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "UOPS_EXECUTED_PORT.PORT_6", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per thread when uops are executed in port 6", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for software prefetch", + "EventCode": "0x4c", + "EventName": "LOAD_HIT_PRE.SW_PF", + "PublicDescription": "Non-SW-prefetch load dispatches that hit fill buffer allocated for S/W prefetch.", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Cycles per core when uops are exectuted in port 6.", - "EventCode": "0xA1", - "Counter": "0,1,2,3", - "UMask": "0x40", - "AnyThread": "1", - "EventName": "UOPS_EXECUTED_PORT.PORT_6_CORE", + "BriefDescription": "Cycles 4 Uops delivered by the LSD, but didn't come from the decoder.", + "CounterMask": "4", + "EventCode": "0xA8", + "EventName": "LSD.CYCLES_4_UOPS", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per core when uops are executed in port 6.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0xA1", - "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "UOPS_DISPATCHED_PORT.PORT_6", + "BriefDescription": "Cycles Uops delivered by the LSD, but didn't come from the decoder.", + "CounterMask": "1", + "EventCode": "0xA8", + "EventName": "LSD.CYCLES_ACTIVE", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per thread when uops are executed in port 6.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "PublicDescription": "Cycles which a uop is dispatched on port 7 in this thread.", - "EventCode": "0xA1", - "Counter": "0,1,2,3", - "UMask": "0x80", - "EventName": "UOPS_EXECUTED_PORT.PORT_7", + "BriefDescription": "Number of Uops delivered by the LSD.", + "EventCode": "0xa8", + "EventName": "LSD.UOPS", + "PublicDescription": "Number of uops delivered by the LSD.", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per thread when uops are executed in port 7", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0xA1", - "Counter": "0,1,2,3", - "UMask": "0x80", - "AnyThread": "1", - "EventName": "UOPS_EXECUTED_PORT.PORT_7_CORE", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per core when uops are dispatched to port 7.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "BriefDescription": "Number of machine clears (nukes) of any type.", + "CounterMask": "1", + "EdgeDetect": "1", + "EventCode": "0xC3", + "EventName": "MACHINE_CLEARS.COUNT", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "EventCode": "0xA1", - "Counter": "0,1,2,3", - "UMask": "0x80", - "EventName": "UOPS_DISPATCHED_PORT.PORT_7", + "BriefDescription": "Cycles there was a Nuke. Account for both thread-specific and All Thread Nukes.", + "EventCode": "0xC3", + "EventName": "MACHINE_CLEARS.CYCLES", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per thread when uops are executed in port 7.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "PublicDescription": "Cycles allocation is stalled due to resource related reason.", - "EventCode": "0xA2", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Errata": "HSD135", - "EventName": "RESOURCE_STALLS.ANY", - "SampleAfterValue": "2000003", - "BriefDescription": "Resource-related stall cycles", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "BriefDescription": "This event counts the number of executed Intel AVX masked load operations that refer to an illegal address range with the mask bits set to 0.", + "EventCode": "0xC3", + "EventName": "MACHINE_CLEARS.MASKMOV", + "SampleAfterValue": "100003", + "UMask": "0x20" }, { - "EventCode": "0xA2", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "RESOURCE_STALLS.RS", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles stalled due to no eligible RS entry available.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "BriefDescription": "Self-modifying code (SMC) detected.", + "EventCode": "0xC3", + "EventName": "MACHINE_CLEARS.SMC", + "PublicDescription": "This event is incremented when self-modifying code (SMC) is detected, which causes a machine clear. Machine clears can have a significant performance impact if they are happening frequently.", + "SampleAfterValue": "100003", + "UMask": "0x4" }, { - "PublicDescription": "This event counts cycles during which no instructions were allocated because no Store Buffers (SB) were available.", - "EventCode": "0xA2", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "RESOURCE_STALLS.SB", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles stalled due to no store buffers available. (not including draining form sync).", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "BriefDescription": "Number of integer Move Elimination candidate uops that were eliminated.", + "EventCode": "0x58", + "EventName": "MOVE_ELIMINATION.INT_ELIMINATED", + "PublicDescription": "Number of integer move elimination candidate uops that were eliminated.", + "SampleAfterValue": "1000003", + "UMask": "0x1" }, { - "EventCode": "0xA2", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "RESOURCE_STALLS.ROB", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles stalled due to re-order buffer full.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "BriefDescription": "Number of integer Move Elimination candidate uops that were not eliminated.", + "EventCode": "0x58", + "EventName": "MOVE_ELIMINATION.INT_NOT_ELIMINATED", + "PublicDescription": "Number of integer move elimination candidate uops that were not eliminated.", + "SampleAfterValue": "1000003", + "UMask": "0x4" }, { - "PublicDescription": "Cycles with pending L2 miss loads. Set Cmask=2 to count cycle.", - "EventCode": "0xA3", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Errata": "HSD78", - "EventName": "CYCLE_ACTIVITY.CYCLES_L2_PENDING", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles with pending L2 cache miss loads.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "BriefDescription": "Number of times any microcode assist is invoked by HW upon uop writeback.", + "EventCode": "0xC1", + "EventName": "OTHER_ASSISTS.ANY_WB_ASSIST", + "PublicDescription": "Number of microcode assists invoked by HW upon uop writeback.", + "SampleAfterValue": "100003", + "UMask": "0x40" }, { - "PublicDescription": "Cycles with pending memory loads. Set Cmask=2 to count cycle.", - "EventCode": "0xA3", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "CYCLE_ACTIVITY.CYCLES_LDM_PENDING", + "BriefDescription": "Resource-related stall cycles", + "Errata": "HSD135", + "EventCode": "0xA2", + "EventName": "RESOURCE_STALLS.ANY", + "PublicDescription": "Cycles allocation is stalled due to resource related reason.", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles with pending memory loads.", - "CounterMask": "2", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "PublicDescription": "This event counts cycles during which no instructions were executed in the execution stage of the pipeline.", - "EventCode": "0xA3", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "CYCLE_ACTIVITY.CYCLES_NO_EXECUTE", + "BriefDescription": "Cycles stalled due to re-order buffer full.", + "EventCode": "0xA2", + "EventName": "RESOURCE_STALLS.ROB", "SampleAfterValue": "2000003", - "BriefDescription": "This event increments by 1 for every cycle where there was no execute for this thread.", - "CounterMask": "4", - "CounterHTOff": "0,1,2,3" + "UMask": "0x10" }, { - "PublicDescription": "Number of loads missed L2.", - "EventCode": "0xA3", - "Counter": "0,1,2,3", - "UMask": "0x5", - "EventName": "CYCLE_ACTIVITY.STALLS_L2_PENDING", + "BriefDescription": "Cycles stalled due to no eligible RS entry available.", + "EventCode": "0xA2", + "EventName": "RESOURCE_STALLS.RS", "SampleAfterValue": "2000003", - "BriefDescription": "Execution stalls due to L2 cache misses.", - "CounterMask": "5", - "CounterHTOff": "0,1,2,3" + "UMask": "0x4" }, { - "PublicDescription": "This event counts cycles during which no instructions were executed in the execution stage of the pipeline and there were memory instructions pending (waiting for data).", - "EventCode": "0xA3", - "Counter": "0,1,2,3", - "UMask": "0x6", - "EventName": "CYCLE_ACTIVITY.STALLS_LDM_PENDING", + "BriefDescription": "Cycles stalled due to no store buffers available. (not including draining form sync).", + "EventCode": "0xA2", + "EventName": "RESOURCE_STALLS.SB", + "PublicDescription": "This event counts cycles during which no instructions were allocated because no Store Buffers (SB) were available.", "SampleAfterValue": "2000003", - "BriefDescription": "Execution stalls due to memory subsystem.", - "CounterMask": "6", - "CounterHTOff": "0,1,2,3" + "UMask": "0x8" }, { - "PublicDescription": "Cycles with pending L1 data cache miss loads. Set Cmask=8 to count cycle.", - "EventCode": "0xA3", - "Counter": "2", - "UMask": "0x8", - "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_PENDING", + "BriefDescription": "Count cases of saving new LBR", + "EventCode": "0xCC", + "EventName": "ROB_MISC_EVENTS.LBR_INSERTS", + "PublicDescription": "Count cases of saving new LBR records by hardware.", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles with pending L1 cache miss loads.", - "CounterMask": "8", - "CounterHTOff": "2" + "UMask": "0x20" }, { - "PublicDescription": "Execution stalls due to L1 data cache miss loads. Set Cmask=0CH.", - "EventCode": "0xA3", - "Counter": "2", - "UMask": "0xc", - "EventName": "CYCLE_ACTIVITY.STALLS_L1D_PENDING", + "BriefDescription": "Cycles when Reservation Station (RS) is empty for the thread", + "EventCode": "0x5E", + "EventName": "RS_EVENTS.EMPTY_CYCLES", + "PublicDescription": "This event counts cycles when the Reservation Station ( RS ) is empty for the thread. The RS is a structure that buffers allocated micro-ops from the Front-end. If there are many cycles when the RS is empty, it may represent an underflow of instructions delivered from the Front-end.", "SampleAfterValue": "2000003", - "BriefDescription": "Execution stalls due to L1 data cache misses", - "CounterMask": "12", - "CounterHTOff": "2" + "UMask": "0x1" }, { - "PublicDescription": "Number of uops delivered by the LSD.", - "EventCode": "0xa8", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "LSD.UOPS", + "BriefDescription": "Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound issues.", + "CounterMask": "1", + "EdgeDetect": "1", + "EventCode": "0x5E", + "EventName": "RS_EVENTS.EMPTY_END", + "Invert": "1", + "SampleAfterValue": "200003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles per thread when uops are executed in port 0.", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_0", "SampleAfterValue": "2000003", - "BriefDescription": "Number of Uops delivered by the LSD.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0xA8", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "LSD.CYCLES_ACTIVE", + "BriefDescription": "Cycles per thread when uops are executed in port 1.", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_1", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles Uops delivered by the LSD, but didn't come from the decoder.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "EventCode": "0xA8", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "LSD.CYCLES_4_UOPS", + "BriefDescription": "Cycles per thread when uops are executed in port 2.", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_2", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles 4 Uops delivered by the LSD, but didn't come from the decoder.", - "CounterMask": "4", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x4" }, { - "EventCode": "0xB1", - "Invert": "1", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Errata": "HSD144, HSD30, HSM31", - "EventName": "UOPS_EXECUTED.STALL_CYCLES", + "BriefDescription": "Cycles per thread when uops are executed in port 3.", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_3", "SampleAfterValue": "2000003", - "BriefDescription": "Counts number of cycles no uops were dispatched to be executed on this thread.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3" + "UMask": "0x8" }, { - "PublicDescription": "This events counts the cycles where at least one uop was executed. It is counted per thread.", - "EventCode": "0xB1", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Errata": "HSD144, HSD30, HSM31", - "EventName": "UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC", + "BriefDescription": "Cycles per thread when uops are executed in port 4.", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_4", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles where at least 1 uop was executed per-thread", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3" + "UMask": "0x10" }, { - "PublicDescription": "This events counts the cycles where at least two uop were executed. It is counted per thread.", - "EventCode": "0xB1", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Errata": "HSD144, HSD30, HSM31", - "EventName": "UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC", + "BriefDescription": "Cycles per thread when uops are executed in port 5.", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_5", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles where at least 2 uops were executed per-thread", - "CounterMask": "2", - "CounterHTOff": "0,1,2,3" + "UMask": "0x20" }, { - "PublicDescription": "This events counts the cycles where at least three uop were executed. It is counted per thread.", - "EventCode": "0xB1", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Errata": "HSD144, HSD30, HSM31", - "EventName": "UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC", + "BriefDescription": "Cycles per thread when uops are executed in port 6.", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_6", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles where at least 3 uops were executed per-thread", - "CounterMask": "3", - "CounterHTOff": "0,1,2,3" + "UMask": "0x40" }, { - "EventCode": "0xB1", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Errata": "HSD144, HSD30, HSM31", - "EventName": "UOPS_EXECUTED.CYCLES_GE_4_UOPS_EXEC", + "BriefDescription": "Cycles per thread when uops are executed in port 7.", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_7", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles where at least 4 uops were executed per-thread.", - "CounterMask": "4", - "CounterHTOff": "0,1,2,3" + "UMask": "0x80" }, { - "PublicDescription": "Counts total number of uops to be executed per-core each cycle.", - "EventCode": "0xB1", - "Counter": "0,1,2,3", - "UMask": "0x2", + "BriefDescription": "Number of uops executed on the core.", "Errata": "HSD30, HSM31", + "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CORE", + "PublicDescription": "Counts total number of uops to be executed per-core each cycle.", "SampleAfterValue": "2000003", - "BriefDescription": "Number of uops executed on the core.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "EventCode": "0xb1", - "Counter": "0,1,2,3", - "UMask": "0x2", + "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.", + "CounterMask": "1", "Errata": "HSD30, HSM31", + "EventCode": "0xb1", "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "EventCode": "0xb1", - "Counter": "0,1,2,3", - "UMask": "0x2", + "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.", + "CounterMask": "2", "Errata": "HSD30, HSM31", + "EventCode": "0xb1", "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.", - "CounterMask": "2", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "EventCode": "0xb1", - "Counter": "0,1,2,3", - "UMask": "0x2", + "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.", + "CounterMask": "3", "Errata": "HSD30, HSM31", + "EventCode": "0xb1", "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.", - "CounterMask": "3", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "EventCode": "0xb1", - "Counter": "0,1,2,3", - "UMask": "0x2", + "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.", + "CounterMask": "4", "Errata": "HSD30, HSM31", + "EventCode": "0xb1", "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.", - "CounterMask": "4", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "EventCode": "0xb1", - "Invert": "1", - "Counter": "0,1,2,3", - "UMask": "0x2", + "BriefDescription": "Cycles with no micro-ops executed from any thread on physical core.", "Errata": "HSD30, HSM31", + "EventCode": "0xb1", "EventName": "UOPS_EXECUTED.CORE_CYCLES_NONE", + "Invert": "1", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles with no micro-ops executed from any thread on physical core.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "PublicDescription": "Number of instructions at retirement.", - "EventCode": "0xC0", - "Counter": "0,1,2,3", - "UMask": "0x0", - "Errata": "HSD11, HSD140", - "EventName": "INST_RETIRED.ANY_P", + "BriefDescription": "Cycles where at least 1 uop was executed per-thread", + "CounterMask": "1", + "Errata": "HSD144, HSD30, HSM31", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC", + "PublicDescription": "This events counts the cycles where at least one uop was executed. It is counted per thread.", "SampleAfterValue": "2000003", - "BriefDescription": "Number of instructions retired. General Counter - architectural event", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "PEBS": "2", - "PublicDescription": "Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution.", - "EventCode": "0xC0", - "Counter": "1", - "UMask": "0x1", - "Errata": "HSD140", - "EventName": "INST_RETIRED.PREC_DIST", + "BriefDescription": "Cycles where at least 2 uops were executed per-thread", + "CounterMask": "2", + "Errata": "HSD144, HSD30, HSM31", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC", + "PublicDescription": "This events counts the cycles where at least two uop were executed. It is counted per thread.", "SampleAfterValue": "2000003", - "BriefDescription": "Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution", - "CounterHTOff": "1" + "UMask": "0x1" }, { - "PEBS": "1", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts FP operations retired. For X87 FP operations that have no exceptions counting also includes flows that have several X87, or flows that use X87 uops in the exception handling.", - "EventCode": "0xC0", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "INST_RETIRED.X87", + "BriefDescription": "Cycles where at least 3 uops were executed per-thread", + "CounterMask": "3", + "Errata": "HSD144, HSD30, HSM31", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC", + "PublicDescription": "This events counts the cycles where at least three uop were executed. It is counted per thread.", "SampleAfterValue": "2000003", - "BriefDescription": "FP operations retired. X87 FP operations that have no exceptions: Counts also flows that have several X87 or flows that use X87 uops in the exception handling.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "PEBS": "1", - "PublicDescription": "", - "EventCode": "0xC1", - "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "OTHER_ASSISTS.ANY_WB_ASSIST", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "BriefDescription": "Cycles where at least 4 uops were executed per-thread.", + "CounterMask": "4", + "Errata": "HSD144, HSD30, HSM31", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CYCLES_GE_4_UOPS_EXEC", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "PEBS": "1", - "EventCode": "0xC2", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_RETIRED.ALL", + "BriefDescription": "Counts number of cycles no uops were dispatched to be executed on this thread.", + "CounterMask": "1", + "Errata": "HSD144, HSD30, HSM31", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.STALL_CYCLES", + "Invert": "1", "SampleAfterValue": "2000003", - "BriefDescription": "Actually retired uops.", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "Data_LA": "1" + "UMask": "0x1" }, { - "PEBS": "1", - "PublicDescription": "", - "EventCode": "0xC2", - "Invert": "1", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_RETIRED.STALL_CYCLES", + "BriefDescription": "Cycles per thread when uops are executed in port 0", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_0", + "PublicDescription": "Cycles which a uop is dispatched on port 0 in this thread.", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles no executable uops retired", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "PEBS": "1", - "PublicDescription": "", - "EventCode": "0xC2", - "Invert": "1", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_RETIRED.TOTAL_CYCLES", + "AnyThread": "1", + "BriefDescription": "Cycles per core when uops are executed in port 0.", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_0_CORE", "SampleAfterValue": "2000003", - "BriefDescription": "Number of cycles using always true condition applied to PEBS uops retired event.", - "CounterMask": "10", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles per thread when uops are executed in port 1", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_1", + "PublicDescription": "Cycles which a uop is dispatched on port 1 in this thread.", + "SampleAfterValue": "2000003", + "UMask": "0x2" }, { - "PEBS": "1", - "PublicDescription": "", - "EventCode": "0xC2", - "Invert": "1", - "Counter": "0,1,2,3", - "UMask": "0x1", "AnyThread": "1", - "EventName": "UOPS_RETIRED.CORE_STALL_CYCLES", + "BriefDescription": "Cycles per core when uops are executed in port 1.", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_1_CORE", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles no executable uops retired on core", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3" + "UMask": "0x2" }, { - "PEBS": "1", - "EventCode": "0xC2", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "UOPS_RETIRED.RETIRE_SLOTS", + "BriefDescription": "Cycles per thread when uops are executed in port 2", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_2", + "PublicDescription": "Cycles which a uop is dispatched on port 2 in this thread.", "SampleAfterValue": "2000003", - "BriefDescription": "Retirement slots used.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x4" }, { - "EventCode": "0xC3", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "MACHINE_CLEARS.CYCLES", + "AnyThread": "1", + "BriefDescription": "Cycles per core when uops are dispatched to port 2.", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_2_CORE", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles there was a Nuke. Account for both thread-specific and All Thread Nukes.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x4" }, { - "EventCode": "0xC3", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EdgeDetect": "1", - "EventName": "MACHINE_CLEARS.COUNT", - "SampleAfterValue": "100003", - "BriefDescription": "Number of machine clears (nukes) of any type.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "BriefDescription": "Cycles per thread when uops are executed in port 3", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_3", + "PublicDescription": "Cycles which a uop is dispatched on port 3 in this thread.", + "SampleAfterValue": "2000003", + "UMask": "0x8" }, { - "PublicDescription": "This event is incremented when self-modifying code (SMC) is detected, which causes a machine clear. Machine clears can have a significant performance impact if they are happening frequently.", - "EventCode": "0xC3", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "MACHINE_CLEARS.SMC", - "SampleAfterValue": "100003", - "BriefDescription": "Self-modifying code (SMC) detected.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "AnyThread": "1", + "BriefDescription": "Cycles per core when uops are dispatched to port 3.", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_3_CORE", + "SampleAfterValue": "2000003", + "UMask": "0x8" }, { - "EventCode": "0xC3", - "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "MACHINE_CLEARS.MASKMOV", - "SampleAfterValue": "100003", - "BriefDescription": "This event counts the number of executed Intel AVX masked load operations that refer to an illegal address range with the mask bits set to 0.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "BriefDescription": "Cycles per thread when uops are executed in port 4", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_4", + "PublicDescription": "Cycles which a uop is dispatched on port 4 in this thread.", + "SampleAfterValue": "2000003", + "UMask": "0x10" }, { - "PublicDescription": "Branch instructions at retirement.", - "EventCode": "0xC4", - "Counter": "0,1,2,3", - "UMask": "0x0", - "EventName": "BR_INST_RETIRED.ALL_BRANCHES", - "SampleAfterValue": "400009", - "BriefDescription": "All (macro) branch instructions retired.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "AnyThread": "1", + "BriefDescription": "Cycles per core when uops are executed in port 4.", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_4_CORE", + "SampleAfterValue": "2000003", + "UMask": "0x10" }, { - "PEBS": "1", - "EventCode": "0xC4", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "BR_INST_RETIRED.CONDITIONAL", - "SampleAfterValue": "400009", - "BriefDescription": "Conditional branch instructions retired.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "BriefDescription": "Cycles per thread when uops are executed in port 5", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_5", + "PublicDescription": "Cycles which a uop is dispatched on port 5 in this thread.", + "SampleAfterValue": "2000003", + "UMask": "0x20" }, { - "PEBS": "1", - "EventCode": "0xC4", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "BR_INST_RETIRED.NEAR_CALL", - "SampleAfterValue": "100003", - "BriefDescription": "Direct and indirect near call instructions retired.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "AnyThread": "1", + "BriefDescription": "Cycles per core when uops are executed in port 5.", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_5_CORE", + "SampleAfterValue": "2000003", + "UMask": "0x20" }, { - "PEBS": "1", - "EventCode": "0xC4", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "BR_INST_RETIRED.NEAR_CALL_R3", - "SampleAfterValue": "100003", - "BriefDescription": "Direct and indirect macro near call instructions retired (captured in ring 3).", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "BriefDescription": "Cycles per thread when uops are executed in port 6", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_6", + "PublicDescription": "Cycles which a uop is dispatched on port 6 in this thread.", + "SampleAfterValue": "2000003", + "UMask": "0x40" }, { - "PEBS": "2", - "EventCode": "0xC4", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "BR_INST_RETIRED.ALL_BRANCHES_PEBS", - "SampleAfterValue": "400009", - "BriefDescription": "All (macro) branch instructions retired.", - "CounterHTOff": "0,1,2,3" + "AnyThread": "1", + "BriefDescription": "Cycles per core when uops are executed in port 6.", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_6_CORE", + "SampleAfterValue": "2000003", + "UMask": "0x40" }, { - "PEBS": "1", - "EventCode": "0xC4", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "BR_INST_RETIRED.NEAR_RETURN", - "SampleAfterValue": "100003", - "BriefDescription": "Return instructions retired.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "BriefDescription": "Cycles per thread when uops are executed in port 7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_7", + "PublicDescription": "Cycles which a uop is dispatched on port 7 in this thread.", + "SampleAfterValue": "2000003", + "UMask": "0x80" }, { - "PEBS": "1", - "PublicDescription": "", - "EventCode": "0xC4", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "BR_INST_RETIRED.NOT_TAKEN", - "SampleAfterValue": "400009", - "BriefDescription": "Counts all not taken macro branch instructions retired.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "AnyThread": "1", + "BriefDescription": "Cycles per core when uops are dispatched to port 7.", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_7_CORE", + "SampleAfterValue": "2000003", + "UMask": "0x80" }, { - "PEBS": "1", - "EventCode": "0xC4", - "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "BR_INST_RETIRED.NEAR_TAKEN", - "SampleAfterValue": "400009", - "BriefDescription": "Taken branch instructions retired.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "BriefDescription": "Uops that Resource Allocation Table (RAT) issues to Reservation Station (RS)", + "EventCode": "0x0E", + "EventName": "UOPS_ISSUED.ANY", + "PublicDescription": "This event counts the number of uops issued by the Front-end of the pipeline to the Back-end. This event is counted at the allocation stage and will count both retired and non-retired uops.", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "PEBS": "1", - "PublicDescription": "", - "EventCode": "0xC4", - "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "BR_INST_RETIRED.FAR_BRANCH", - "SampleAfterValue": "100003", - "BriefDescription": "Counts the number of far branch instructions retired.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "AnyThread": "1", + "BriefDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for all threads.", + "CounterMask": "1", + "EventCode": "0x0E", + "EventName": "UOPS_ISSUED.CORE_STALL_CYCLES", + "Invert": "1", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "PublicDescription": "Mispredicted branch instructions at retirement.", - "EventCode": "0xC5", - "Counter": "0,1,2,3", - "UMask": "0x0", - "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", - "SampleAfterValue": "400009", - "BriefDescription": "All mispredicted macro branch instructions retired.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "BriefDescription": "Number of flags-merge uops being allocated. Such uops considered perf sensitive; added by GSR u-arch.", + "EventCode": "0x0E", + "EventName": "UOPS_ISSUED.FLAGS_MERGE", + "PublicDescription": "Number of flags-merge uops allocated. Such uops add delay.", + "SampleAfterValue": "2000003", + "UMask": "0x10" + }, + { + "BriefDescription": "Number of Multiply packed/scalar single precision uops allocated", + "EventCode": "0x0E", + "EventName": "UOPS_ISSUED.SINGLE_MUL", + "PublicDescription": "Number of multiply packed/scalar single precision uops allocated.", + "SampleAfterValue": "2000003", + "UMask": "0x40" + }, + { + "BriefDescription": "Number of slow LEA uops being allocated. A uop is generally considered SlowLea if it has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not.", + "EventCode": "0x0E", + "EventName": "UOPS_ISSUED.SLOW_LEA", + "PublicDescription": "Number of slow LEA or similar uops allocated. Such uop has 3 sources (for example, 2 sources + immediate) regardless of whether it is a result of LEA instruction or not.", + "SampleAfterValue": "2000003", + "UMask": "0x20" + }, + { + "BriefDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread.", + "CounterMask": "1", + "EventCode": "0x0E", + "EventName": "UOPS_ISSUED.STALL_CYCLES", + "Invert": "1", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { + "BriefDescription": "Actually retired uops.", + "EventCode": "0xC2", + "EventName": "UOPS_RETIRED.ALL", "PEBS": "1", - "EventCode": "0xC5", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "BR_MISP_RETIRED.CONDITIONAL", - "SampleAfterValue": "400009", - "BriefDescription": "Mispredicted conditional branch instructions retired.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "PublicDescription": "Counts the number of micro-ops retired. Use Cmask=1 and invert to count active cycles or stalled cycles.", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "PEBS": "2", - "PublicDescription": "This event counts all mispredicted branch instructions retired. This is a precise event.", - "EventCode": "0xC5", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "BR_MISP_RETIRED.ALL_BRANCHES_PEBS", - "SampleAfterValue": "400009", - "BriefDescription": "Mispredicted macro branch instructions retired.", - "CounterHTOff": "0,1,2,3" + "AnyThread": "1", + "BriefDescription": "Cycles without actually retired uops.", + "CounterMask": "1", + "EventCode": "0xC2", + "EventName": "UOPS_RETIRED.CORE_STALL_CYCLES", + "Invert": "1", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { + "BriefDescription": "Retirement slots used.", + "EventCode": "0xC2", + "EventName": "UOPS_RETIRED.RETIRE_SLOTS", "PEBS": "1", - "EventCode": "0xC5", - "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "BR_MISP_RETIRED.NEAR_TAKEN", - "SampleAfterValue": "400009", - "BriefDescription": "number of near branch instructions retired that were mispredicted and taken.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "PublicDescription": "This event counts the number of retirement slots used each cycle. There are potentially 4 slots that can be used each cycle - meaning, 4 uops or 4 instructions could retire each cycle.", + "SampleAfterValue": "2000003", + "UMask": "0x2" }, { - "PublicDescription": "Count cases of saving new LBR records by hardware.", - "EventCode": "0xCC", - "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "ROB_MISC_EVENTS.LBR_INSERTS", + "BriefDescription": "Cycles without actually retired uops.", + "CounterMask": "1", + "EventCode": "0xC2", + "EventName": "UOPS_RETIRED.STALL_CYCLES", + "Invert": "1", "SampleAfterValue": "2000003", - "BriefDescription": "Count cases of saving new LBR", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "PublicDescription": "Number of front end re-steers due to BPU misprediction.", - "EventCode": "0xe6", - "Counter": "0,1,2,3", - "UMask": "0x1f", - "EventName": "BACLEARS.ANY", - "SampleAfterValue": "100003", - "BriefDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "BriefDescription": "Cycles with less than 10 actually retired uops.", + "CounterMask": "16", + "EventCode": "0xC2", + "EventName": "UOPS_RETIRED.TOTAL_CYCLES", + "Invert": "1", + "SampleAfterValue": "2000003", + "UMask": "0x1" } -]
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