diff options
Diffstat (limited to '')
| -rw-r--r-- | tools/perf/pmu-events/arch/x86/westmereep-sp/cache.json | 2559 |
1 files changed, 1021 insertions, 1538 deletions
diff --git a/tools/perf/pmu-events/arch/x86/westmereep-sp/cache.json b/tools/perf/pmu-events/arch/x86/westmereep-sp/cache.json index dad20f0e3cac..d025e2c0cf1c 100644 --- a/tools/perf/pmu-events/arch/x86/westmereep-sp/cache.json +++ b/tools/perf/pmu-events/arch/x86/westmereep-sp/cache.json @@ -1,3233 +1,2716 @@ [ { + "BriefDescription": "Cycles L1D locked", "EventCode": "0x63", - "Counter": "0,1", - "UMask": "0x2", "EventName": "CACHE_LOCK_CYCLES.L1D", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles L1D locked" + "UMask": "0x2" }, { + "BriefDescription": "Cycles L1D and L2 locked", "EventCode": "0x63", - "Counter": "0,1", - "UMask": "0x1", "EventName": "CACHE_LOCK_CYCLES.L1D_L2", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles L1D and L2 locked" + "UMask": "0x1" }, { + "BriefDescription": "L1D cache lines replaced in M state", "EventCode": "0x51", - "Counter": "0,1", - "UMask": "0x4", "EventName": "L1D.M_EVICT", "SampleAfterValue": "2000000", - "BriefDescription": "L1D cache lines replaced in M state" + "UMask": "0x4" }, { + "BriefDescription": "L1D cache lines allocated in the M state", "EventCode": "0x51", - "Counter": "0,1", - "UMask": "0x2", "EventName": "L1D.M_REPL", "SampleAfterValue": "2000000", - "BriefDescription": "L1D cache lines allocated in the M state" + "UMask": "0x2" }, { + "BriefDescription": "L1D snoop eviction of cache lines in M state", "EventCode": "0x51", - "Counter": "0,1", - "UMask": "0x8", "EventName": "L1D.M_SNOOP_EVICT", "SampleAfterValue": "2000000", - "BriefDescription": "L1D snoop eviction of cache lines in M state" + "UMask": "0x8" }, { + "BriefDescription": "L1 data cache lines allocated", "EventCode": "0x51", - "Counter": "0,1", - "UMask": "0x1", "EventName": "L1D.REPL", "SampleAfterValue": "2000000", - "BriefDescription": "L1 data cache lines allocated" + "UMask": "0x1" }, { + "BriefDescription": "L1D prefetch load lock accepted in fill buffer", "EventCode": "0x52", - "Counter": "0,1", - "UMask": "0x1", "EventName": "L1D_CACHE_PREFETCH_LOCK_FB_HIT", "SampleAfterValue": "2000000", - "BriefDescription": "L1D prefetch load lock accepted in fill buffer" + "UMask": "0x1" }, { + "BriefDescription": "L1D hardware prefetch misses", "EventCode": "0x4E", - "Counter": "0,1", - "UMask": "0x2", "EventName": "L1D_PREFETCH.MISS", "SampleAfterValue": "200000", - "BriefDescription": "L1D hardware prefetch misses" + "UMask": "0x2" }, { + "BriefDescription": "L1D hardware prefetch requests", "EventCode": "0x4E", - "Counter": "0,1", - "UMask": "0x1", "EventName": "L1D_PREFETCH.REQUESTS", "SampleAfterValue": "200000", - "BriefDescription": "L1D hardware prefetch requests" + "UMask": "0x1" }, { + "BriefDescription": "L1D hardware prefetch requests triggered", "EventCode": "0x4E", - "Counter": "0,1", - "UMask": "0x4", "EventName": "L1D_PREFETCH.TRIGGERS", "SampleAfterValue": "200000", - "BriefDescription": "L1D hardware prefetch requests triggered" + "UMask": "0x4" }, { + "BriefDescription": "L1 writebacks to L2 in E state", "EventCode": "0x28", - "Counter": "0,1,2,3", - "UMask": "0x4", "EventName": "L1D_WB_L2.E_STATE", "SampleAfterValue": "100000", - "BriefDescription": "L1 writebacks to L2 in E state" + "UMask": "0x4" }, { + "BriefDescription": "L1 writebacks to L2 in I state (misses)", "EventCode": "0x28", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "L1D_WB_L2.I_STATE", "SampleAfterValue": "100000", - "BriefDescription": "L1 writebacks to L2 in I state (misses)" + "UMask": "0x1" }, { + "BriefDescription": "All L1 writebacks to L2", "EventCode": "0x28", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "L1D_WB_L2.M_STATE", + "EventName": "L1D_WB_L2.MESI", "SampleAfterValue": "100000", - "BriefDescription": "L1 writebacks to L2 in M state" + "UMask": "0xf" }, { + "BriefDescription": "L1 writebacks to L2 in M state", "EventCode": "0x28", - "Counter": "0,1,2,3", - "UMask": "0xf", - "EventName": "L1D_WB_L2.MESI", + "EventName": "L1D_WB_L2.M_STATE", "SampleAfterValue": "100000", - "BriefDescription": "All L1 writebacks to L2" + "UMask": "0x8" }, { + "BriefDescription": "L1 writebacks to L2 in S state", "EventCode": "0x28", - "Counter": "0,1,2,3", - "UMask": "0x2", "EventName": "L1D_WB_L2.S_STATE", "SampleAfterValue": "100000", - "BriefDescription": "L1 writebacks to L2 in S state" + "UMask": "0x2" }, { + "BriefDescription": "All L2 data requests", "EventCode": "0x26", - "Counter": "0,1,2,3", - "UMask": "0xff", "EventName": "L2_DATA_RQSTS.ANY", "SampleAfterValue": "200000", - "BriefDescription": "All L2 data requests" + "UMask": "0xff" }, { + "BriefDescription": "L2 data demand loads in E state", "EventCode": "0x26", - "Counter": "0,1,2,3", - "UMask": "0x4", "EventName": "L2_DATA_RQSTS.DEMAND.E_STATE", "SampleAfterValue": "200000", - "BriefDescription": "L2 data demand loads in E state" + "UMask": "0x4" }, { + "BriefDescription": "L2 data demand loads in I state (misses)", "EventCode": "0x26", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "L2_DATA_RQSTS.DEMAND.I_STATE", "SampleAfterValue": "200000", - "BriefDescription": "L2 data demand loads in I state (misses)" + "UMask": "0x1" }, { + "BriefDescription": "L2 data demand requests", "EventCode": "0x26", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "L2_DATA_RQSTS.DEMAND.M_STATE", + "EventName": "L2_DATA_RQSTS.DEMAND.MESI", "SampleAfterValue": "200000", - "BriefDescription": "L2 data demand loads in M state" + "UMask": "0xf" }, { + "BriefDescription": "L2 data demand loads in M state", "EventCode": "0x26", - "Counter": "0,1,2,3", - "UMask": "0xf", - "EventName": "L2_DATA_RQSTS.DEMAND.MESI", + "EventName": "L2_DATA_RQSTS.DEMAND.M_STATE", "SampleAfterValue": "200000", - "BriefDescription": "L2 data demand requests" + "UMask": "0x8" }, { + "BriefDescription": "L2 data demand loads in S state", "EventCode": "0x26", - "Counter": "0,1,2,3", - "UMask": "0x2", "EventName": "L2_DATA_RQSTS.DEMAND.S_STATE", "SampleAfterValue": "200000", - "BriefDescription": "L2 data demand loads in S state" + "UMask": "0x2" }, { + "BriefDescription": "L2 data prefetches in E state", "EventCode": "0x26", - "Counter": "0,1,2,3", - "UMask": "0x40", "EventName": "L2_DATA_RQSTS.PREFETCH.E_STATE", "SampleAfterValue": "200000", - "BriefDescription": "L2 data prefetches in E state" + "UMask": "0x40" }, { + "BriefDescription": "L2 data prefetches in the I state (misses)", "EventCode": "0x26", - "Counter": "0,1,2,3", - "UMask": "0x10", "EventName": "L2_DATA_RQSTS.PREFETCH.I_STATE", "SampleAfterValue": "200000", - "BriefDescription": "L2 data prefetches in the I state (misses)" + "UMask": "0x10" }, { + "BriefDescription": "All L2 data prefetches", "EventCode": "0x26", - "Counter": "0,1,2,3", - "UMask": "0x80", - "EventName": "L2_DATA_RQSTS.PREFETCH.M_STATE", + "EventName": "L2_DATA_RQSTS.PREFETCH.MESI", "SampleAfterValue": "200000", - "BriefDescription": "L2 data prefetches in M state" + "UMask": "0xf0" }, { + "BriefDescription": "L2 data prefetches in M state", "EventCode": "0x26", - "Counter": "0,1,2,3", - "UMask": "0xf0", - "EventName": "L2_DATA_RQSTS.PREFETCH.MESI", + "EventName": "L2_DATA_RQSTS.PREFETCH.M_STATE", "SampleAfterValue": "200000", - "BriefDescription": "All L2 data prefetches" + "UMask": "0x80" }, { + "BriefDescription": "L2 data prefetches in the S state", "EventCode": "0x26", - "Counter": "0,1,2,3", - "UMask": "0x20", "EventName": "L2_DATA_RQSTS.PREFETCH.S_STATE", "SampleAfterValue": "200000", - "BriefDescription": "L2 data prefetches in the S state" + "UMask": "0x20" }, { + "BriefDescription": "L2 lines allocated", "EventCode": "0xF1", - "Counter": "0,1,2,3", - "UMask": "0x7", "EventName": "L2_LINES_IN.ANY", "SampleAfterValue": "100000", - "BriefDescription": "L2 lines alloacated" + "UMask": "0x7" }, { + "BriefDescription": "L2 lines allocated in the E state", "EventCode": "0xF1", - "Counter": "0,1,2,3", - "UMask": "0x4", "EventName": "L2_LINES_IN.E_STATE", "SampleAfterValue": "100000", - "BriefDescription": "L2 lines allocated in the E state" + "UMask": "0x4" }, { + "BriefDescription": "L2 lines allocated in the S state", "EventCode": "0xF1", - "Counter": "0,1,2,3", - "UMask": "0x2", "EventName": "L2_LINES_IN.S_STATE", "SampleAfterValue": "100000", - "BriefDescription": "L2 lines allocated in the S state" + "UMask": "0x2" }, { + "BriefDescription": "L2 lines evicted", "EventCode": "0xF2", - "Counter": "0,1,2,3", - "UMask": "0xf", "EventName": "L2_LINES_OUT.ANY", "SampleAfterValue": "100000", - "BriefDescription": "L2 lines evicted" + "UMask": "0xf" }, { + "BriefDescription": "L2 lines evicted by a demand request", "EventCode": "0xF2", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "L2_LINES_OUT.DEMAND_CLEAN", "SampleAfterValue": "100000", - "BriefDescription": "L2 lines evicted by a demand request" + "UMask": "0x1" }, { + "BriefDescription": "L2 modified lines evicted by a demand request", "EventCode": "0xF2", - "Counter": "0,1,2,3", - "UMask": "0x2", "EventName": "L2_LINES_OUT.DEMAND_DIRTY", "SampleAfterValue": "100000", - "BriefDescription": "L2 modified lines evicted by a demand request" + "UMask": "0x2" }, { + "BriefDescription": "L2 lines evicted by a prefetch request", "EventCode": "0xF2", - "Counter": "0,1,2,3", - "UMask": "0x4", "EventName": "L2_LINES_OUT.PREFETCH_CLEAN", "SampleAfterValue": "100000", - "BriefDescription": "L2 lines evicted by a prefetch request" + "UMask": "0x4" }, { + "BriefDescription": "L2 modified lines evicted by a prefetch request", "EventCode": "0xF2", - "Counter": "0,1,2,3", - "UMask": "0x8", "EventName": "L2_LINES_OUT.PREFETCH_DIRTY", "SampleAfterValue": "100000", - "BriefDescription": "L2 modified lines evicted by a prefetch request" + "UMask": "0x8" }, { + "BriefDescription": "L2 instruction fetches", "EventCode": "0x24", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "L2_RQSTS.IFETCH_HIT", + "EventName": "L2_RQSTS.IFETCHES", "SampleAfterValue": "200000", - "BriefDescription": "L2 instruction fetch hits" + "UMask": "0x30" }, { + "BriefDescription": "L2 instruction fetch hits", "EventCode": "0x24", - "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "L2_RQSTS.IFETCH_MISS", + "EventName": "L2_RQSTS.IFETCH_HIT", "SampleAfterValue": "200000", - "BriefDescription": "L2 instruction fetch misses" + "UMask": "0x10" }, { + "BriefDescription": "L2 instruction fetch misses", "EventCode": "0x24", - "Counter": "0,1,2,3", - "UMask": "0x30", - "EventName": "L2_RQSTS.IFETCHES", + "EventName": "L2_RQSTS.IFETCH_MISS", "SampleAfterValue": "200000", - "BriefDescription": "L2 instruction fetches" + "UMask": "0x20" }, { + "BriefDescription": "L2 load hits", "EventCode": "0x24", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "L2_RQSTS.LD_HIT", "SampleAfterValue": "200000", - "BriefDescription": "L2 load hits" + "UMask": "0x1" }, { + "BriefDescription": "L2 load misses", "EventCode": "0x24", - "Counter": "0,1,2,3", - "UMask": "0x2", "EventName": "L2_RQSTS.LD_MISS", "SampleAfterValue": "200000", - "BriefDescription": "L2 load misses" + "UMask": "0x2" }, { + "BriefDescription": "L2 requests", "EventCode": "0x24", - "Counter": "0,1,2,3", - "UMask": "0x3", "EventName": "L2_RQSTS.LOADS", "SampleAfterValue": "200000", - "BriefDescription": "L2 requests" + "UMask": "0x3" }, { + "BriefDescription": "All L2 misses", "EventCode": "0x24", - "Counter": "0,1,2,3", - "UMask": "0xaa", "EventName": "L2_RQSTS.MISS", "SampleAfterValue": "200000", - "BriefDescription": "All L2 misses" + "UMask": "0xaa" }, { + "BriefDescription": "All L2 prefetches", "EventCode": "0x24", - "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "L2_RQSTS.PREFETCH_HIT", + "EventName": "L2_RQSTS.PREFETCHES", "SampleAfterValue": "200000", - "BriefDescription": "L2 prefetch hits" + "UMask": "0xc0" }, { + "BriefDescription": "L2 prefetch hits", "EventCode": "0x24", - "Counter": "0,1,2,3", - "UMask": "0x80", - "EventName": "L2_RQSTS.PREFETCH_MISS", + "EventName": "L2_RQSTS.PREFETCH_HIT", "SampleAfterValue": "200000", - "BriefDescription": "L2 prefetch misses" + "UMask": "0x40" }, { + "BriefDescription": "L2 prefetch misses", "EventCode": "0x24", - "Counter": "0,1,2,3", - "UMask": "0xc0", - "EventName": "L2_RQSTS.PREFETCHES", + "EventName": "L2_RQSTS.PREFETCH_MISS", "SampleAfterValue": "200000", - "BriefDescription": "All L2 prefetches" + "UMask": "0x80" }, { + "BriefDescription": "All L2 requests", "EventCode": "0x24", - "Counter": "0,1,2,3", - "UMask": "0xff", "EventName": "L2_RQSTS.REFERENCES", "SampleAfterValue": "200000", - "BriefDescription": "All L2 requests" + "UMask": "0xff" }, { + "BriefDescription": "L2 RFO requests", "EventCode": "0x24", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "L2_RQSTS.RFO_HIT", + "EventName": "L2_RQSTS.RFOS", "SampleAfterValue": "200000", - "BriefDescription": "L2 RFO hits" + "UMask": "0xc" }, { + "BriefDescription": "L2 RFO hits", "EventCode": "0x24", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "L2_RQSTS.RFO_MISS", + "EventName": "L2_RQSTS.RFO_HIT", "SampleAfterValue": "200000", - "BriefDescription": "L2 RFO misses" + "UMask": "0x4" }, { + "BriefDescription": "L2 RFO misses", "EventCode": "0x24", - "Counter": "0,1,2,3", - "UMask": "0xc", - "EventName": "L2_RQSTS.RFOS", + "EventName": "L2_RQSTS.RFO_MISS", "SampleAfterValue": "200000", - "BriefDescription": "L2 RFO requests" + "UMask": "0x8" }, { + "BriefDescription": "All L2 transactions", "EventCode": "0xF0", - "Counter": "0,1,2,3", - "UMask": "0x80", "EventName": "L2_TRANSACTIONS.ANY", "SampleAfterValue": "200000", - "BriefDescription": "All L2 transactions" + "UMask": "0x80" }, { + "BriefDescription": "L2 fill transactions", "EventCode": "0xF0", - "Counter": "0,1,2,3", - "UMask": "0x20", "EventName": "L2_TRANSACTIONS.FILL", "SampleAfterValue": "200000", - "BriefDescription": "L2 fill transactions" + "UMask": "0x20" }, { + "BriefDescription": "L2 instruction fetch transactions", "EventCode": "0xF0", - "Counter": "0,1,2,3", - "UMask": "0x4", "EventName": "L2_TRANSACTIONS.IFETCH", "SampleAfterValue": "200000", - "BriefDescription": "L2 instruction fetch transactions" + "UMask": "0x4" }, { + "BriefDescription": "L1D writeback to L2 transactions", "EventCode": "0xF0", - "Counter": "0,1,2,3", - "UMask": "0x10", "EventName": "L2_TRANSACTIONS.L1D_WB", "SampleAfterValue": "200000", - "BriefDescription": "L1D writeback to L2 transactions" + "UMask": "0x10" }, { + "BriefDescription": "L2 Load transactions", "EventCode": "0xF0", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "L2_TRANSACTIONS.LOAD", "SampleAfterValue": "200000", - "BriefDescription": "L2 Load transactions" + "UMask": "0x1" }, { + "BriefDescription": "L2 prefetch transactions", "EventCode": "0xF0", - "Counter": "0,1,2,3", - "UMask": "0x8", "EventName": "L2_TRANSACTIONS.PREFETCH", "SampleAfterValue": "200000", - "BriefDescription": "L2 prefetch transactions" + "UMask": "0x8" }, { + "BriefDescription": "L2 RFO transactions", "EventCode": "0xF0", - "Counter": "0,1,2,3", - "UMask": "0x2", "EventName": "L2_TRANSACTIONS.RFO", "SampleAfterValue": "200000", - "BriefDescription": "L2 RFO transactions" + "UMask": "0x2" }, { + "BriefDescription": "L2 writeback to LLC transactions", "EventCode": "0xF0", - "Counter": "0,1,2,3", - "UMask": "0x40", "EventName": "L2_TRANSACTIONS.WB", "SampleAfterValue": "200000", - "BriefDescription": "L2 writeback to LLC transactions" + "UMask": "0x40" }, { + "BriefDescription": "L2 demand lock RFOs in E state", "EventCode": "0x27", - "Counter": "0,1,2,3", - "UMask": "0x40", "EventName": "L2_WRITE.LOCK.E_STATE", "SampleAfterValue": "100000", - "BriefDescription": "L2 demand lock RFOs in E state" + "UMask": "0x40" }, { + "BriefDescription": "All demand L2 lock RFOs that hit the cache", "EventCode": "0x27", - "Counter": "0,1,2,3", - "UMask": "0xe0", "EventName": "L2_WRITE.LOCK.HIT", "SampleAfterValue": "100000", - "BriefDescription": "All demand L2 lock RFOs that hit the cache" + "UMask": "0xe0" }, { + "BriefDescription": "L2 demand lock RFOs in I state (misses)", "EventCode": "0x27", - "Counter": "0,1,2,3", - "UMask": "0x10", "EventName": "L2_WRITE.LOCK.I_STATE", "SampleAfterValue": "100000", - "BriefDescription": "L2 demand lock RFOs in I state (misses)" + "UMask": "0x10" }, { + "BriefDescription": "All demand L2 lock RFOs", "EventCode": "0x27", - "Counter": "0,1,2,3", - "UMask": "0x80", - "EventName": "L2_WRITE.LOCK.M_STATE", + "EventName": "L2_WRITE.LOCK.MESI", "SampleAfterValue": "100000", - "BriefDescription": "L2 demand lock RFOs in M state" + "UMask": "0xf0" }, { + "BriefDescription": "L2 demand lock RFOs in M state", "EventCode": "0x27", - "Counter": "0,1,2,3", - "UMask": "0xf0", - "EventName": "L2_WRITE.LOCK.MESI", + "EventName": "L2_WRITE.LOCK.M_STATE", "SampleAfterValue": "100000", - "BriefDescription": "All demand L2 lock RFOs" + "UMask": "0x80" }, { + "BriefDescription": "L2 demand lock RFOs in S state", "EventCode": "0x27", - "Counter": "0,1,2,3", - "UMask": "0x20", "EventName": "L2_WRITE.LOCK.S_STATE", "SampleAfterValue": "100000", - "BriefDescription": "L2 demand lock RFOs in S state" + "UMask": "0x20" }, { + "BriefDescription": "All L2 demand store RFOs that hit the cache", "EventCode": "0x27", - "Counter": "0,1,2,3", - "UMask": "0xe", "EventName": "L2_WRITE.RFO.HIT", "SampleAfterValue": "100000", - "BriefDescription": "All L2 demand store RFOs that hit the cache" + "UMask": "0xe" }, { + "BriefDescription": "L2 demand store RFOs in I state (misses)", "EventCode": "0x27", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "L2_WRITE.RFO.I_STATE", "SampleAfterValue": "100000", - "BriefDescription": "L2 demand store RFOs in I state (misses)" + "UMask": "0x1" }, { + "BriefDescription": "All L2 demand store RFOs", "EventCode": "0x27", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "L2_WRITE.RFO.M_STATE", + "EventName": "L2_WRITE.RFO.MESI", "SampleAfterValue": "100000", - "BriefDescription": "L2 demand store RFOs in M state" + "UMask": "0xf" }, { + "BriefDescription": "L2 demand store RFOs in M state", "EventCode": "0x27", - "Counter": "0,1,2,3", - "UMask": "0xf", - "EventName": "L2_WRITE.RFO.MESI", + "EventName": "L2_WRITE.RFO.M_STATE", "SampleAfterValue": "100000", - "BriefDescription": "All L2 demand store RFOs" + "UMask": "0x8" }, { + "BriefDescription": "L2 demand store RFOs in S state", "EventCode": "0x27", - "Counter": "0,1,2,3", - "UMask": "0x2", "EventName": "L2_WRITE.RFO.S_STATE", "SampleAfterValue": "100000", - "BriefDescription": "L2 demand store RFOs in S state" + "UMask": "0x2" }, { + "BriefDescription": "Longest latency cache miss", "EventCode": "0x2E", - "Counter": "0,1,2,3", - "UMask": "0x41", "EventName": "LONGEST_LAT_CACHE.MISS", "SampleAfterValue": "100000", - "BriefDescription": "Longest latency cache miss" + "UMask": "0x41" }, { + "BriefDescription": "Longest latency cache reference", "EventCode": "0x2E", - "Counter": "0,1,2,3", - "UMask": "0x4f", "EventName": "LONGEST_LAT_CACHE.REFERENCE", "SampleAfterValue": "200000", - "BriefDescription": "Longest latency cache reference" + "UMask": "0x4f" }, { - "PEBS": "1", + "BriefDescription": "Memory instructions retired above 0 clocks (Precise Event)", "EventCode": "0xB", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "MEM_INST_RETIRED.LOADS", + "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_0", + "MSRIndex": "0x3F6", + "PEBS": "2", "SampleAfterValue": "2000000", - "BriefDescription": "Instructions retired which contains a load (Precise Event)" + "UMask": "0x10" + }, + { + "BriefDescription": "Memory instructions retired above 1024 clocks (Precise Event)", + "EventCode": "0xB", + "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_1024", + "MSRIndex": "0x3F6", + "MSRValue": "0x400", + "PEBS": "2", + "SampleAfterValue": "100", + "UMask": "0x10" + }, + { + "BriefDescription": "Memory instructions retired above 128 clocks (Precise Event)", + "EventCode": "0xB", + "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_128", + "MSRIndex": "0x3F6", + "MSRValue": "0x80", + "PEBS": "2", + "SampleAfterValue": "1000", + "UMask": "0x10" + }, + { + "BriefDescription": "Memory instructions retired above 16 clocks (Precise Event)", + "EventCode": "0xB", + "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16", + "MSRIndex": "0x3F6", + "MSRValue": "0x10", + "PEBS": "2", + "SampleAfterValue": "10000", + "UMask": "0x10" + }, + { + "BriefDescription": "Memory instructions retired above 16384 clocks (Precise Event)", + "EventCode": "0xB", + "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16384", + "MSRIndex": "0x3F6", + "MSRValue": "0x4000", + "PEBS": "2", + "SampleAfterValue": "5", + "UMask": "0x10" + }, + { + "BriefDescription": "Memory instructions retired above 2048 clocks (Precise Event)", + "EventCode": "0xB", + "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_2048", + "MSRIndex": "0x3F6", + "MSRValue": "0x800", + "PEBS": "2", + "SampleAfterValue": "50", + "UMask": "0x10" + }, + { + "BriefDescription": "Memory instructions retired above 256 clocks (Precise Event)", + "EventCode": "0xB", + "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_256", + "MSRIndex": "0x3F6", + "MSRValue": "0x100", + "PEBS": "2", + "SampleAfterValue": "500", + "UMask": "0x10" + }, + { + "BriefDescription": "Memory instructions retired above 32 clocks (Precise Event)", + "EventCode": "0xB", + "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32", + "MSRIndex": "0x3F6", + "MSRValue": "0x20", + "PEBS": "2", + "SampleAfterValue": "5000", + "UMask": "0x10" + }, + { + "BriefDescription": "Memory instructions retired above 32768 clocks (Precise Event)", + "EventCode": "0xB", + "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32768", + "MSRIndex": "0x3F6", + "MSRValue": "0x8000", + "PEBS": "2", + "SampleAfterValue": "3", + "UMask": "0x10" + }, + { + "BriefDescription": "Memory instructions retired above 4 clocks (Precise Event)", + "EventCode": "0xB", + "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4", + "MSRIndex": "0x3F6", + "MSRValue": "0x4", + "PEBS": "2", + "SampleAfterValue": "50000", + "UMask": "0x10" + }, + { + "BriefDescription": "Memory instructions retired above 4096 clocks (Precise Event)", + "EventCode": "0xB", + "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4096", + "MSRIndex": "0x3F6", + "MSRValue": "0x1000", + "PEBS": "2", + "SampleAfterValue": "20", + "UMask": "0x10" + }, + { + "BriefDescription": "Memory instructions retired above 512 clocks (Precise Event)", + "EventCode": "0xB", + "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_512", + "MSRIndex": "0x3F6", + "MSRValue": "0x200", + "PEBS": "2", + "SampleAfterValue": "200", + "UMask": "0x10" + }, + { + "BriefDescription": "Memory instructions retired above 64 clocks (Precise Event)", + "EventCode": "0xB", + "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_64", + "MSRIndex": "0x3F6", + "MSRValue": "0x40", + "PEBS": "2", + "SampleAfterValue": "2000", + "UMask": "0x10" + }, + { + "BriefDescription": "Memory instructions retired above 8 clocks (Precise Event)", + "EventCode": "0xB", + "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8", + "MSRIndex": "0x3F6", + "MSRValue": "0x8", + "PEBS": "2", + "SampleAfterValue": "20000", + "UMask": "0x10" + }, + { + "BriefDescription": "Memory instructions retired above 8192 clocks (Precise Event)", + "EventCode": "0xB", + "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8192", + "MSRIndex": "0x3F6", + "MSRValue": "0x2000", + "PEBS": "2", + "SampleAfterValue": "10", + "UMask": "0x10" }, { + "BriefDescription": "Instructions retired which contains a load (Precise Event)", + "EventCode": "0xB", + "EventName": "MEM_INST_RETIRED.LOADS", "PEBS": "1", + "SampleAfterValue": "2000000", + "UMask": "0x1" + }, + { + "BriefDescription": "Instructions retired which contains a store (Precise Event)", "EventCode": "0xB", - "Counter": "0,1,2,3", - "UMask": "0x2", "EventName": "MEM_INST_RETIRED.STORES", + "PEBS": "1", "SampleAfterValue": "2000000", - "BriefDescription": "Instructions retired which contains a store (Precise Event)" + "UMask": "0x2" }, { - "PEBS": "1", + "BriefDescription": "Retired loads that miss L1D and hit an previously allocated LFB (Precise Event)", "EventCode": "0xCB", - "Counter": "0,1,2,3", - "UMask": "0x40", "EventName": "MEM_LOAD_RETIRED.HIT_LFB", + "PEBS": "1", "SampleAfterValue": "200000", - "BriefDescription": "Retired loads that miss L1D and hit an previously allocated LFB (Precise Event)" + "UMask": "0x40" }, { - "PEBS": "1", + "BriefDescription": "Retired loads that hit the L1 data cache (Precise Event)", "EventCode": "0xCB", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "MEM_LOAD_RETIRED.L1D_HIT", + "PEBS": "1", "SampleAfterValue": "2000000", - "BriefDescription": "Retired loads that hit the L1 data cache (Precise Event)" + "UMask": "0x1" }, { - "PEBS": "1", + "BriefDescription": "Retired loads that hit the L2 cache (Precise Event)", "EventCode": "0xCB", - "Counter": "0,1,2,3", - "UMask": "0x2", "EventName": "MEM_LOAD_RETIRED.L2_HIT", + "PEBS": "1", "SampleAfterValue": "200000", - "BriefDescription": "Retired loads that hit the L2 cache (Precise Event)" + "UMask": "0x2" }, { - "PEBS": "1", + "BriefDescription": "Retired loads that miss the LLC cache (Precise Event)", "EventCode": "0xCB", - "Counter": "0,1,2,3", - "UMask": "0x10", "EventName": "MEM_LOAD_RETIRED.LLC_MISS", + "PEBS": "1", "SampleAfterValue": "10000", - "BriefDescription": "Retired loads that miss the LLC cache (Precise Event)" + "UMask": "0x10" }, { - "PEBS": "1", + "BriefDescription": "Retired loads that hit valid versions in the LLC cache (Precise Event)", "EventCode": "0xCB", - "Counter": "0,1,2,3", - "UMask": "0x4", "EventName": "MEM_LOAD_RETIRED.LLC_UNSHARED_HIT", + "PEBS": "1", "SampleAfterValue": "40000", - "BriefDescription": "Retired loads that hit valid versions in the LLC cache (Precise Event)" + "UMask": "0x4" }, { - "PEBS": "1", + "BriefDescription": "Retired loads that hit sibling core's L2 in modified or unmodified states (Precise Event)", "EventCode": "0xCB", - "Counter": "0,1,2,3", - "UMask": "0x8", "EventName": "MEM_LOAD_RETIRED.OTHER_CORE_L2_HIT_HITM", + "PEBS": "1", "SampleAfterValue": "40000", - "BriefDescription": "Retired loads that hit sibling core's L2 in modified or unmodified states (Precise Event)" + "UMask": "0x8" }, { - "PEBS": "1", + "BriefDescription": "Load instructions retired with a data source of local DRAM or locally homed remote hitm (Precise Event)", "EventCode": "0xF", - "Counter": "0,1,2,3", - "UMask": "0x10", "EventName": "MEM_UNCORE_RETIRED.LOCAL_DRAM", + "PEBS": "1", "SampleAfterValue": "10000", - "BriefDescription": "Load instructions retired with a data source of local DRAM or locally homed remote hitm (Precise Event)" + "UMask": "0x10" }, { - "PEBS": "1", + "BriefDescription": "Load instructions retired that HIT modified data in sibling core (Precise Event)", "EventCode": "0xF", - "Counter": "0,1,2,3", - "UMask": "0x2", "EventName": "MEM_UNCORE_RETIRED.OTHER_CORE_L2_HITM", + "PEBS": "1", "SampleAfterValue": "40000", - "BriefDescription": "Load instructions retired that HIT modified data in sibling core (Precise Event)" + "UMask": "0x2" }, { - "PEBS": "1", + "BriefDescription": "Load instructions retired remote cache HIT data source (Precise Event)", "EventCode": "0xF", - "Counter": "0,1,2,3", - "UMask": "0x8", "EventName": "MEM_UNCORE_RETIRED.REMOTE_CACHE_LOCAL_HOME_HIT", + "PEBS": "1", "SampleAfterValue": "20000", - "BriefDescription": "Load instructions retired remote cache HIT data source (Precise Event)" + "UMask": "0x8" }, { - "PEBS": "1", + "BriefDescription": "Load instructions retired remote DRAM and remote home-remote cache HITM (Precise Event)", "EventCode": "0xF", - "Counter": "0,1,2,3", - "UMask": "0x20", "EventName": "MEM_UNCORE_RETIRED.REMOTE_DRAM", + "PEBS": "1", "SampleAfterValue": "10000", - "BriefDescription": "Load instructions retired remote DRAM and remote home-remote cache HITM (Precise Event)" + "UMask": "0x20" }, { - "PEBS": "1", + "BriefDescription": "Load instructions retired IO (Precise Event)", "EventCode": "0xF", - "Counter": "0,1,2,3", - "UMask": "0x80", "EventName": "MEM_UNCORE_RETIRED.UNCACHEABLE", + "PEBS": "1", "SampleAfterValue": "4000", - "BriefDescription": "Load instructions retired IO (Precise Event)" + "UMask": "0x80" }, { + "BriefDescription": "All offcore requests", "EventCode": "0xB0", - "Counter": "0,1,2,3", - "UMask": "0x80", "EventName": "OFFCORE_REQUESTS.ANY", "SampleAfterValue": "100000", - "BriefDescription": "All offcore requests" + "UMask": "0x80" }, { + "BriefDescription": "Offcore read requests", "EventCode": "0xB0", - "Counter": "0,1,2,3", - "UMask": "0x8", "EventName": "OFFCORE_REQUESTS.ANY.READ", "SampleAfterValue": "100000", - "BriefDescription": "Offcore read requests" + "UMask": "0x8" }, { + "BriefDescription": "Offcore RFO requests", "EventCode": "0xB0", - "Counter": "0,1,2,3", - "UMask": "0x10", "EventName": "OFFCORE_REQUESTS.ANY.RFO", "SampleAfterValue": "100000", - "BriefDescription": "Offcore RFO requests" + "UMask": "0x10" }, { + "BriefDescription": "Offcore demand code read requests", "EventCode": "0xB0", - "Counter": "0,1,2,3", - "UMask": "0x2", "EventName": "OFFCORE_REQUESTS.DEMAND.READ_CODE", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand code read requests" + "UMask": "0x2" }, { + "BriefDescription": "Offcore demand data read requests", "EventCode": "0xB0", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_REQUESTS.DEMAND.READ_DATA", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data read requests" + "UMask": "0x1" }, { + "BriefDescription": "Offcore demand RFO requests", "EventCode": "0xB0", - "Counter": "0,1,2,3", - "UMask": "0x4", "EventName": "OFFCORE_REQUESTS.DEMAND.RFO", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand RFO requests" + "UMask": "0x4" }, { + "BriefDescription": "Offcore L1 data cache writebacks", "EventCode": "0xB0", - "Counter": "0,1,2,3", - "UMask": "0x40", "EventName": "OFFCORE_REQUESTS.L1D_WRITEBACK", "SampleAfterValue": "100000", - "BriefDescription": "Offcore L1 data cache writebacks" + "UMask": "0x40" }, { + "BriefDescription": "Offcore uncached memory accesses", "EventCode": "0xB0", - "Counter": "0,1,2,3", - "UMask": "0x20", "EventName": "OFFCORE_REQUESTS.UNCACHED_MEM", "SampleAfterValue": "100000", - "BriefDescription": "Offcore uncached memory accesses" + "UMask": "0x20" }, { + "BriefDescription": "Outstanding offcore reads", "EventCode": "0x60", - "UMask": "0x8", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ANY.READ", "SampleAfterValue": "2000000", - "BriefDescription": "Outstanding offcore reads" + "UMask": "0x8" }, { + "BriefDescription": "Cycles offcore reads busy", + "CounterMask": "1", "EventCode": "0x60", - "UMask": "0x8", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ANY.READ_NOT_EMPTY", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles offcore reads busy", - "CounterMask": "1" + "UMask": "0x8" }, { + "BriefDescription": "Outstanding offcore demand code reads", "EventCode": "0x60", - "UMask": "0x2", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_CODE", "SampleAfterValue": "2000000", - "BriefDescription": "Outstanding offcore demand code reads" + "UMask": "0x2" }, { + "BriefDescription": "Cycles offcore demand code read busy", + "CounterMask": "1", "EventCode": "0x60", - "UMask": "0x2", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_CODE_NOT_EMPTY", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles offcore demand code read busy", - "CounterMask": "1" + "UMask": "0x2" }, { + "BriefDescription": "Outstanding offcore demand data reads", "EventCode": "0x60", - "UMask": "0x1", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_DATA", "SampleAfterValue": "2000000", - "BriefDescription": "Outstanding offcore demand data reads" + "UMask": "0x1" }, { + "BriefDescription": "Cycles offcore demand data read busy", + "CounterMask": "1", "EventCode": "0x60", - "UMask": "0x1", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_DATA_NOT_EMPTY", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles offcore demand data read busy", - "CounterMask": "1" + "UMask": "0x1" }, { + "BriefDescription": "Outstanding offcore demand RFOs", "EventCode": "0x60", - "UMask": "0x4", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.RFO", "SampleAfterValue": "2000000", - "BriefDescription": "Outstanding offcore demand RFOs" + "UMask": "0x4" }, { + "BriefDescription": "Cycles offcore demand RFOs busy", + "CounterMask": "1", "EventCode": "0x60", - "UMask": "0x4", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.RFO_NOT_EMPTY", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles offcore demand RFOs busy", - "CounterMask": "1" + "UMask": "0x4" }, { + "BriefDescription": "Offcore requests blocked due to Super Queue full", "EventCode": "0xB2", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_REQUESTS_SQ_FULL", "SampleAfterValue": "100000", - "BriefDescription": "Offcore requests blocked due to Super Queue full" - }, - { - "EventCode": "0xF4", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "SQ_MISC.LRU_HINTS", - "SampleAfterValue": "2000000", - "BriefDescription": "Super Queue LRU hints sent to LLC" - }, - { - "EventCode": "0xF4", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "SQ_MISC.SPLIT_LOCK", - "SampleAfterValue": "2000000", - "BriefDescription": "Super Queue lock splits across a cache line" - }, - { - "EventCode": "0x6", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "STORE_BLOCKS.AT_RET", - "SampleAfterValue": "200000", - "BriefDescription": "Loads delayed with at-Retirement block code" - }, - { - "EventCode": "0x6", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "STORE_BLOCKS.L1D_BLOCK", - "SampleAfterValue": "200000", - "BriefDescription": "Cacheable loads delayed with L1D block code" - }, - { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x0", - "Counter": "3", - "UMask": "0x10", - "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_0", - "MSRIndex": "0x3F6", - "SampleAfterValue": "2000000", - "BriefDescription": "Memory instructions retired above 0 clocks (Precise Event)" - }, - { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x400", - "Counter": "3", - "UMask": "0x10", - "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_1024", - "MSRIndex": "0x3F6", - "SampleAfterValue": "100", - "BriefDescription": "Memory instructions retired above 1024 clocks (Precise Event)" - }, - { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x80", - "Counter": "3", - "UMask": "0x10", - "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_128", - "MSRIndex": "0x3F6", - "SampleAfterValue": "1000", - "BriefDescription": "Memory instructions retired above 128 clocks (Precise Event)" - }, - { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x10", - "Counter": "3", - "UMask": "0x10", - "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16", - "MSRIndex": "0x3F6", - "SampleAfterValue": "10000", - "BriefDescription": "Memory instructions retired above 16 clocks (Precise Event)" - }, - { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x4000", - "Counter": "3", - "UMask": "0x10", - "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16384", - "MSRIndex": "0x3F6", - "SampleAfterValue": "5", - "BriefDescription": "Memory instructions retired above 16384 clocks (Precise Event)" - }, - { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x800", - "Counter": "3", - "UMask": "0x10", - "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_2048", - "MSRIndex": "0x3F6", - "SampleAfterValue": "50", - "BriefDescription": "Memory instructions retired above 2048 clocks (Precise Event)" - }, - { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x100", - "Counter": "3", - "UMask": "0x10", - "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_256", - "MSRIndex": "0x3F6", - "SampleAfterValue": "500", - "BriefDescription": "Memory instructions retired above 256 clocks (Precise Event)" - }, - { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x20", - "Counter": "3", - "UMask": "0x10", - "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32", - "MSRIndex": "0x3F6", - "SampleAfterValue": "5000", - "BriefDescription": "Memory instructions retired above 32 clocks (Precise Event)" - }, - { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x8000", - "Counter": "3", - "UMask": "0x10", - "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32768", - "MSRIndex": "0x3F6", - "SampleAfterValue": "3", - "BriefDescription": "Memory instructions retired above 32768 clocks (Precise Event)" - }, - { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x4", - "Counter": "3", - "UMask": "0x10", - "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4", - "MSRIndex": "0x3F6", - "SampleAfterValue": "50000", - "BriefDescription": "Memory instructions retired above 4 clocks (Precise Event)" - }, - { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x1000", - "Counter": "3", - "UMask": "0x10", - "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4096", - "MSRIndex": "0x3F6", - "SampleAfterValue": "20", - "BriefDescription": "Memory instructions retired above 4096 clocks (Precise Event)" - }, - { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x200", - "Counter": "3", - "UMask": "0x10", - "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_512", - "MSRIndex": "0x3F6", - "SampleAfterValue": "200", - "BriefDescription": "Memory instructions retired above 512 clocks (Precise Event)" - }, - { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x40", - "Counter": "3", - "UMask": "0x10", - "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_64", - "MSRIndex": "0x3F6", - "SampleAfterValue": "2000", - "BriefDescription": "Memory instructions retired above 64 clocks (Precise Event)" - }, - { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x8", - "Counter": "3", - "UMask": "0x10", - "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8", - "MSRIndex": "0x3F6", - "SampleAfterValue": "20000", - "BriefDescription": "Memory instructions retired above 8 clocks (Precise Event)" - }, - { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x2000", - "Counter": "3", - "UMask": "0x10", - "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8192", - "MSRIndex": "0x3F6", - "SampleAfterValue": "10", - "BriefDescription": "Memory instructions retired above 8192 clocks (Precise Event)" + "UMask": "0x1" }, { + "BriefDescription": "Offcore data reads satisfied by any cache or DRAM", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x7F11", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x7F11", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads satisfied by any cache or DRAM", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "All offcore data reads", "EventCode": "0xB7, 0xBB", - "MSRValue": "0xFF11", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xFF11", "SampleAfterValue": "100000", - "BriefDescription": "All offcore data reads", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore data reads satisfied by the IO, CSR, MMIO unit", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x8011", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.ANY_DATA.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8011", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads satisfied by the IO, CSR, MMIO unit", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore data reads satisfied by the LLC and not found in a sibling core", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x111", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x111", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads satisfied by the LLC and not found in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore data reads satisfied by the LLC and HIT in a sibling core", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x211", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x211", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads satisfied by the LLC and HIT in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore data reads satisfied by the LLC and HITM in a sibling core", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x411", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x411", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads satisfied by the LLC and HITM in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore data reads satisfied by the LLC", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x711", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x711", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads satisfied by the LLC", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore data reads satisfied by the LLC or local DRAM", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2711", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2711", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads satisfied by the LLC or local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore data reads satisfied by a remote cache", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1811", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1811", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads satisfied by a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore data reads satisfied by a remote cache or remote DRAM", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x5811", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x5811", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads satisfied by a remote cache or remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore data reads that HIT in a remote cache", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1011", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1011", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads that HIT in a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore data reads that HITM in a remote cache", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x811", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x811", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads that HITM in a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore code reads satisfied by any cache or DRAM", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x7F44", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x7F44", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code reads satisfied by any cache or DRAM", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "All offcore code reads", "EventCode": "0xB7, 0xBB", - "MSRValue": "0xFF44", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xFF44", "SampleAfterValue": "100000", - "BriefDescription": "All offcore code reads", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore code reads satisfied by the IO, CSR, MMIO unit", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x8044", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8044", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code reads satisfied by the IO, CSR, MMIO unit", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore code reads satisfied by the LLC and not found in a sibling core", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x144", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x144", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code reads satisfied by the LLC and not found in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore code reads satisfied by the LLC and HIT in a sibling core", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x244", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x244", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code reads satisfied by the LLC and HIT in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore code reads satisfied by the LLC and HITM in a sibling core", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x444", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x444", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code reads satisfied by the LLC and HITM in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore code reads satisfied by the LLC", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x744", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x744", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code reads satisfied by the LLC", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore code reads satisfied by the LLC or local DRAM", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2744", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2744", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code reads satisfied by the LLC or local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore code reads satisfied by a remote cache", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1844", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1844", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code reads satisfied by a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore code reads satisfied by a remote cache or remote DRAM", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x5844", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x5844", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code reads satisfied by a remote cache or remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore code reads that HIT in a remote cache", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1044", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1044", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code reads that HIT in a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore code reads that HITM in a remote cache", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x844", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x844", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code reads that HITM in a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore requests satisfied by any cache or DRAM", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x7FFF", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x7FFF", "SampleAfterValue": "100000", - "BriefDescription": "Offcore requests satisfied by any cache or DRAM", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "All offcore requests", "EventCode": "0xB7, 0xBB", - "MSRValue": "0xFFFF", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xFFFF", "SampleAfterValue": "100000", - "BriefDescription": "All offcore requests", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore requests satisfied by the IO, CSR, MMIO unit", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x80FF", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x80FF", "SampleAfterValue": "100000", - "BriefDescription": "Offcore requests satisfied by the IO, CSR, MMIO unit", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore requests satisfied by the LLC and not found in a sibling core", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1FF", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1FF", "SampleAfterValue": "100000", - "BriefDescription": "Offcore requests satisfied by the LLC and not found in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore requests satisfied by the LLC and HIT in a sibling core", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2FF", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2FF", "SampleAfterValue": "100000", - "BriefDescription": "Offcore requests satisfied by the LLC and HIT in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore requests satisfied by the LLC and HITM in a sibling core", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x4FF", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4FF", "SampleAfterValue": "100000", - "BriefDescription": "Offcore requests satisfied by the LLC and HITM in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore requests satisfied by the LLC", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x7FF", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x7FF", "SampleAfterValue": "100000", - "BriefDescription": "Offcore requests satisfied by the LLC", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore requests satisfied by the LLC or local DRAM", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x27FF", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x27FF", "SampleAfterValue": "100000", - "BriefDescription": "Offcore requests satisfied by the LLC or local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore requests satisfied by a remote cache", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x18FF", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x18FF", "SampleAfterValue": "100000", - "BriefDescription": "Offcore requests satisfied by a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore requests satisfied by a remote cache or remote DRAM", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x58FF", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x58FF", "SampleAfterValue": "100000", - "BriefDescription": "Offcore requests satisfied by a remote cache or remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore requests that HIT in a remote cache", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10FF", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10FF", "SampleAfterValue": "100000", - "BriefDescription": "Offcore requests that HIT in a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore requests that HITM in a remote cache", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x8FF", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8FF", "SampleAfterValue": "100000", - "BriefDescription": "Offcore requests that HITM in a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore RFO requests satisfied by any cache or DRAM", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x7F22", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x7F22", "SampleAfterValue": "100000", - "BriefDescription": "Offcore RFO requests satisfied by any cache or DRAM", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "All offcore RFO requests", "EventCode": "0xB7, 0xBB", - "MSRValue": "0xFF22", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xFF22", "SampleAfterValue": "100000", - "BriefDescription": "All offcore RFO requests", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore RFO requests satisfied by the IO, CSR, MMIO unit", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x8022", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.ANY_RFO.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8022", "SampleAfterValue": "100000", - "BriefDescription": "Offcore RFO requests satisfied by the IO, CSR, MMIO unit", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore RFO requests satisfied by the LLC and not found in a sibling core", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x122", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x122", "SampleAfterValue": "100000", - "BriefDescription": "Offcore RFO requests satisfied by the LLC and not found in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore RFO requests satisfied by the LLC and HIT in a sibling core", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x222", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x222", "SampleAfterValue": "100000", - "BriefDescription": "Offcore RFO requests satisfied by the LLC and HIT in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore RFO requests satisfied by the LLC and HITM in a sibling core", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x422", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x422", "SampleAfterValue": "100000", - "BriefDescription": "Offcore RFO requests satisfied by the LLC and HITM in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore RFO requests satisfied by the LLC", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x722", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x722", "SampleAfterValue": "100000", - "BriefDescription": "Offcore RFO requests satisfied by the LLC", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore RFO requests satisfied by the LLC or local DRAM", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2722", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2722", "SampleAfterValue": "100000", - "BriefDescription": "Offcore RFO requests satisfied by the LLC or local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore RFO requests satisfied by a remote cache", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1822", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1822", "SampleAfterValue": "100000", - "BriefDescription": "Offcore RFO requests satisfied by a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore RFO requests satisfied by a remote cache or remote DRAM", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x5822", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x5822", "SampleAfterValue": "100000", - "BriefDescription": "Offcore RFO requests satisfied by a remote cache or remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore RFO requests that HIT in a remote cache", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1022", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1022", "SampleAfterValue": "100000", - "BriefDescription": "Offcore RFO requests that HIT in a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore RFO requests that HITM in a remote cache", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x822", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x822", "SampleAfterValue": "100000", - "BriefDescription": "Offcore RFO requests that HITM in a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore writebacks to any cache or DRAM.", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x7F08", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.COREWB.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x7F08", "SampleAfterValue": "100000", - "BriefDescription": "Offcore writebacks to any cache or DRAM.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "All offcore writebacks", "EventCode": "0xB7, 0xBB", - "MSRValue": "0xFF08", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.COREWB.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xFF08", "SampleAfterValue": "100000", - "BriefDescription": "All offcore writebacks", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore writebacks to the IO, CSR, MMIO unit.", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x8008", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.COREWB.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8008", "SampleAfterValue": "100000", - "BriefDescription": "Offcore writebacks to the IO, CSR, MMIO unit.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore writebacks to the LLC and not found in a sibling core", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x108", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x108", "SampleAfterValue": "100000", - "BriefDescription": "Offcore writebacks to the LLC and not found in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore writebacks to the LLC and HITM in a sibling core", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x408", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x408", "SampleAfterValue": "100000", - "BriefDescription": "Offcore writebacks to the LLC and HITM in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore writebacks to the LLC", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x708", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x708", "SampleAfterValue": "100000", - "BriefDescription": "Offcore writebacks to the LLC", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore writebacks to the LLC or local DRAM", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2708", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2708", "SampleAfterValue": "100000", - "BriefDescription": "Offcore writebacks to the LLC or local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore writebacks to a remote cache", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1808", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1808", "SampleAfterValue": "100000", - "BriefDescription": "Offcore writebacks to a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore writebacks to a remote cache or remote DRAM", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x5808", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x5808", "SampleAfterValue": "100000", - "BriefDescription": "Offcore writebacks to a remote cache or remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore writebacks that HIT in a remote cache", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1008", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1008", "SampleAfterValue": "100000", - "BriefDescription": "Offcore writebacks that HIT in a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore writebacks that HITM in a remote cache", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x808", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x808", "SampleAfterValue": "100000", - "BriefDescription": "Offcore writebacks that HITM in a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore code or data read requests satisfied by any cache or DRAM.", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x7F77", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x7F77", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code or data read requests satisfied by any cache or DRAM.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "All offcore code or data read requests", "EventCode": "0xB7, 0xBB", - "MSRValue": "0xFF77", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xFF77", "SampleAfterValue": "100000", - "BriefDescription": "All offcore code or data read requests", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore code or data read requests satisfied by the IO, CSR, MMIO unit.", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x8077", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8077", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code or data read requests satisfied by the IO, CSR, MMIO unit.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore code or data read requests satisfied by the LLC and not found in a sibling core", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x177", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x177", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code or data read requests satisfied by the LLC and not found in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore code or data read requests satisfied by the LLC and HIT in a sibling core", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x277", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x277", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code or data read requests satisfied by the LLC and HIT in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore code or data read requests satisfied by the LLC and HITM in a sibling core", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x477", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x477", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code or data read requests satisfied by the LLC and HITM in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore code or data read requests satisfied by the LLC", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x777", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x777", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code or data read requests satisfied by the LLC", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore code or data read requests satisfied by the LLC or local DRAM", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2777", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2777", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code or data read requests satisfied by the LLC or local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore code or data read requests satisfied by a remote cache", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1877", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1877", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code or data read requests satisfied by a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore code or data read requests satisfied by a remote cache or remote DRAM", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x5877", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x5877", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code or data read requests satisfied by a remote cache or remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore code or data read requests that HIT in a remote cache", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1077", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1077", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code or data read requests that HIT in a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore code or data read requests that HITM in a remote cache", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x877", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x877", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code or data read requests that HITM in a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore request = all data, response = any cache_dram", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x7F33", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x7F33", "SampleAfterValue": "100000", - "BriefDescription": "Offcore request = all data, response = any cache_dram", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore request = all data, response = any location", "EventCode": "0xB7, 0xBB", - "MSRValue": "0xFF33", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xFF33", "SampleAfterValue": "100000", - "BriefDescription": "Offcore request = all data, response = any location", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the IO, CSR, MMIO unit", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x8033", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.DATA_IN.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8033", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads, RFO's and prefetches satisfied by the IO, CSR, MMIO unit", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the LLC and not found in a sibling core", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x133", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x133", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads, RFO's and prefetches statisfied by the LLC and not found in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the LLC and HIT in a sibling core", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x233", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x233", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads, RFO's and prefetches satisfied by the LLC and HIT in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the LLC and HITM in a sibling core", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x433", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x433", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads, RFO's and prefetches satisfied by the LLC and HITM in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore request = all data, response = local cache", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x733", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x733", "SampleAfterValue": "100000", - "BriefDescription": "Offcore request = all data, response = local cache", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore request = all data, response = local cache or dram", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2733", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2733", "SampleAfterValue": "100000", - "BriefDescription": "Offcore request = all data, response = local cache or dram", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore request = all data, response = remote cache", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1833", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1833", "SampleAfterValue": "100000", - "BriefDescription": "Offcore request = all data, response = remote cache", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore request = all data, response = remote cache or dram", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x5833", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x5833", "SampleAfterValue": "100000", - "BriefDescription": "Offcore request = all data, response = remote cache or dram", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore data reads, RFOs, and prefetches that HIT in a remote cache", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1033", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1033", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads, RFO's and prefetches that HIT in a remote cache ", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore data reads, RFOs, and prefetches that HITM in a remote cache", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x833", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x833", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads, RFO's and prefetches that HITM in a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore demand data requests satisfied by any cache or DRAM", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x7F03", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x7F03", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data requests satisfied by any cache or DRAM", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "All offcore demand data requests", "EventCode": "0xB7, 0xBB", - "MSRValue": "0xFF03", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xFF03", "SampleAfterValue": "100000", - "BriefDescription": "All offcore demand data requests", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore demand data requests satisfied by the IO, CSR, MMIO unit.", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x8003", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8003", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data requests satisfied by the IO, CSR, MMIO unit.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore demand data requests satisfied by the LLC and not found in a sibling core", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x103", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x103", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data requests satisfied by the LLC and not found in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore demand data requests satisfied by the LLC and HIT in a sibling core", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x203", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x203", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data requests satisfied by the LLC and HIT in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore demand data requests satisfied by the LLC and HITM in a sibling core", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x403", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x403", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data requests satisfied by the LLC and HITM in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore demand data requests satisfied by the LLC", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x703", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x703", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data requests satisfied by the LLC", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore demand data requests satisfied by the LLC or local DRAM", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2703", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2703", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data requests satisfied by the LLC or local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore demand data requests satisfied by a remote cache", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1803", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1803", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data requests satisfied by a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore demand data requests satisfied by a remote cache or remote DRAM", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x5803", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x5803", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data requests satisfied by a remote cache or remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore demand data requests that HIT in a remote cache", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1003", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1003", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data requests that HIT in a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore demand data requests that HITM in a remote cache", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x803", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x803", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data requests that HITM in a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore demand data reads satisfied by any cache or DRAM.", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x7F01", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x7F01", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data reads satisfied by any cache or DRAM.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "All offcore demand data reads", "EventCode": "0xB7, 0xBB", - "MSRValue": "0xFF01", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xFF01", "SampleAfterValue": "100000", - "BriefDescription": "All offcore demand data reads", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore demand data reads satisfied by the IO, CSR, MMIO unit", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x8001", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8001", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data reads satisfied by the IO, CSR, MMIO unit", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore demand data reads satisfied by the LLC and not found in a sibling core", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x101", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x101", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data reads satisfied by the LLC and not found in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore demand data reads satisfied by the LLC and HIT in a sibling core", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x201", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x201", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data reads satisfied by the LLC and HIT in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore demand data reads satisfied by the LLC and HITM in a sibling core", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x401", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x401", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data reads satisfied by the LLC and HITM in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore demand data reads satisfied by the LLC", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x701", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x701", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data reads satisfied by the LLC", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore demand data reads satisfied by the LLC or local DRAM", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2701", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2701", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data reads satisfied by the LLC or local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore demand data reads satisfied by a remote cache", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1801", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1801", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data reads satisfied by a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore demand data reads satisfied by a remote cache or remote DRAM", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x5801", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x5801", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data reads satisfied by a remote cache or remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore demand data reads that HIT in a remote cache", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1001", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1001", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data reads that HIT in a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore demand data reads that HITM in a remote cache", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x801", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x801", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data reads that HITM in a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore demand code reads satisfied by any cache or DRAM.", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x7F04", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x7F04", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand code reads satisfied by any cache or DRAM.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "All offcore demand code reads", "EventCode": "0xB7, 0xBB", - "MSRValue": "0xFF04", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xFF04", "SampleAfterValue": "100000", - "BriefDescription": "All offcore demand code reads", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore demand code reads satisfied by the IO, CSR, MMIO unit", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x8004", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8004", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand code reads satisfied by the IO, CSR, MMIO unit", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore demand code reads satisfied by the LLC and not found in a sibling core", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x104", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x104", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand code reads satisfied by the LLC and not found in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore demand code reads satisfied by the LLC and HIT in a sibling core", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x204", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x204", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand code reads satisfied by the LLC and HIT in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore demand code reads satisfied by the LLC and HITM in a sibling core", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x404", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x404", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand code reads satisfied by the LLC and HITM in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore demand code reads satisfied by the LLC", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x704", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x704", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand code reads satisfied by the LLC", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore demand code reads satisfied by the LLC or local DRAM", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2704", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2704", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand code reads satisfied by the LLC or local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore demand code reads satisfied by a remote cache", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1804", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1804", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand code reads satisfied by a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore demand code reads satisfied by a remote cache or remote DRAM", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x5804", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x5804", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand code reads satisfied by a remote cache or remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore demand code reads that HIT in a remote cache", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1004", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1004", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand code reads that HIT in a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore demand code reads that HITM in a remote cache", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x804", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x804", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand code reads that HITM in a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore demand RFO requests satisfied by any cache or DRAM.", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x7F02", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x7F02", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand RFO requests satisfied by any cache or DRAM.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "All offcore demand RFO requests", "EventCode": "0xB7, 0xBB", - "MSRValue": "0xFF02", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xFF02", "SampleAfterValue": "100000", - "BriefDescription": "All offcore demand RFO requests", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore demand RFO requests satisfied by the IO, CSR, MMIO unit", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x8002", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8002", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand RFO requests satisfied by the IO, CSR, MMIO unit", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore demand RFO requests satisfied by the LLC and not found in a sibling core", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x102", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x102", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand RFO requests satisfied by the LLC and not found in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore demand RFO requests satisfied by the LLC and HIT in a sibling core", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x202", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x202", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand RFO requests satisfied by the LLC and HIT in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore demand RFO requests satisfied by the LLC and HITM in a sibling core", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x402", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x402", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand RFO requests satisfied by the LLC and HITM in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore demand RFO requests satisfied by the LLC", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x702", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x702", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand RFO requests satisfied by the LLC", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore demand RFO requests satisfied by the LLC or local DRAM", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2702", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2702", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand RFO requests satisfied by the LLC or local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore demand RFO requests satisfied by a remote cache", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1802", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1802", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand RFO requests satisfied by a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore demand RFO requests satisfied by a remote cache or remote DRAM", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x5802", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x5802", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand RFO requests satisfied by a remote cache or remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore demand RFO requests that HIT in a remote cache", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1002", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1002", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand RFO requests that HIT in a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore demand RFO requests that HITM in a remote cache", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x802", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x802", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand RFO requests that HITM in a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore other requests satisfied by any cache or DRAM.", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x7F80", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.OTHER.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x7F80", "SampleAfterValue": "100000", - "BriefDescription": "Offcore other requests satisfied by any cache or DRAM.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "All offcore other requests", "EventCode": "0xB7, 0xBB", - "MSRValue": "0xFF80", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.OTHER.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xFF80", "SampleAfterValue": "100000", - "BriefDescription": "All offcore other requests", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore other requests satisfied by the IO, CSR, MMIO unit", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x8080", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.OTHER.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8080", "SampleAfterValue": "100000", - "BriefDescription": "Offcore other requests satisfied by the IO, CSR, MMIO unit", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore other requests satisfied by the LLC and not found in a sibling core", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x180", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x180", "SampleAfterValue": "100000", - "BriefDescription": "Offcore other requests satisfied by the LLC and not found in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore other requests satisfied by the LLC and HIT in a sibling core", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x280", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x280", "SampleAfterValue": "100000", - "BriefDescription": "Offcore other requests satisfied by the LLC and HIT in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore other requests satisfied by the LLC and HITM in a sibling core", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x480", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x480", "SampleAfterValue": "100000", - "BriefDescription": "Offcore other requests satisfied by the LLC and HITM in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore other requests satisfied by the LLC", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x780", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.OTHER.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x780", "SampleAfterValue": "100000", - "BriefDescription": "Offcore other requests satisfied by the LLC", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore other requests satisfied by the LLC or local DRAM", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2780", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.OTHER.LOCAL_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2780", "SampleAfterValue": "100000", - "BriefDescription": "Offcore other requests satisfied by the LLC or local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore other requests satisfied by a remote cache", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1880", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1880", "SampleAfterValue": "100000", - "BriefDescription": "Offcore other requests satisfied by a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore other requests satisfied by a remote cache or remote DRAM", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x5880", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x5880", "SampleAfterValue": "100000", - "BriefDescription": "Offcore other requests satisfied by a remote cache or remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore other requests that HIT in a remote cache", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1080", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1080", "SampleAfterValue": "100000", - "BriefDescription": "Offcore other requests that HIT in a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore other requests that HITM in a remote cache", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x880", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x880", "SampleAfterValue": "100000", - "BriefDescription": "Offcore other requests that HITM in a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore prefetch data requests satisfied by any cache or DRAM", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x7F50", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x7F50", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data requests satisfied by any cache or DRAM", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "All offcore prefetch data requests", "EventCode": "0xB7, 0xBB", - "MSRValue": "0xFF50", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xFF50", "SampleAfterValue": "100000", - "BriefDescription": "All offcore prefetch data requests", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore prefetch data requests satisfied by the IO, CSR, MMIO unit.", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x8050", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.PF_DATA.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8050", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data requests satisfied by the IO, CSR, MMIO unit.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore prefetch data requests satisfied by the LLC and not found in a sibling core", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x150", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x150", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data requests satisfied by the LLC and not found in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore prefetch data requests satisfied by the LLC and HIT in a sibling core", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x250", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x250", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data requests satisfied by the LLC and HIT in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore prefetch data requests satisfied by the LLC and HITM in a sibling core", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x450", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x450", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data requests satisfied by the LLC and HITM in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore prefetch data requests satisfied by the LLC", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x750", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x750", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data requests satisfied by the LLC", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore prefetch data requests satisfied by the LLC or local DRAM", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2750", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2750", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data requests satisfied by the LLC or local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore prefetch data requests satisfied by a remote cache", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1850", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1850", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data requests satisfied by a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore prefetch data requests satisfied by a remote cache or remote DRAM", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x5850", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x5850", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data requests satisfied by a remote cache or remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore prefetch data requests that HIT in a remote cache", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1050", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1050", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data requests that HIT in a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore prefetch data requests that HITM in a remote cache", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x850", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x850", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data requests that HITM in a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore prefetch data reads satisfied by any cache or DRAM.", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x7F10", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x7F10", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data reads satisfied by any cache or DRAM.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "All offcore prefetch data reads", "EventCode": "0xB7, 0xBB", - "MSRValue": "0xFF10", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xFF10", "SampleAfterValue": "100000", - "BriefDescription": "All offcore prefetch data reads", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore prefetch data reads satisfied by the IO, CSR, MMIO unit", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x8010", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8010", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data reads satisfied by the IO, CSR, MMIO unit", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore prefetch data reads satisfied by the LLC and not found in a sibling core", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x110", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x110", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data reads satisfied by the LLC and not found in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore prefetch data reads satisfied by the LLC and HIT in a sibling core", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x210", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x210", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data reads satisfied by the LLC and HIT in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore prefetch data reads satisfied by the LLC and HITM in a sibling core", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x410", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x410", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data reads satisfied by the LLC and HITM in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore prefetch data reads satisfied by the LLC", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x710", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x710", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data reads satisfied by the LLC", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore prefetch data reads satisfied by the LLC or local DRAM", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2710", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2710", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data reads satisfied by the LLC or local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore prefetch data reads satisfied by a remote cache", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1810", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1810", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data reads satisfied by a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore prefetch data reads satisfied by a remote cache or remote DRAM", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x5810", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x5810", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data reads satisfied by a remote cache or remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore prefetch data reads that HIT in a remote cache", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1010", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1010", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data reads that HIT in a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore prefetch data reads that HITM in a remote cache", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x810", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x810", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data reads that HITM in a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore prefetch code reads satisfied by any cache or DRAM.", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x7F40", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x7F40", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch code reads satisfied by any cache or DRAM.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "All offcore prefetch code reads", "EventCode": "0xB7, 0xBB", - "MSRValue": "0xFF40", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xFF40", "SampleAfterValue": "100000", - "BriefDescription": "All offcore prefetch code reads", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore prefetch code reads satisfied by the IO, CSR, MMIO unit", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x8040", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8040", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch code reads satisfied by the IO, CSR, MMIO unit", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore prefetch code reads satisfied by the LLC and not found in a sibling core", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x140", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x140", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch code reads satisfied by the LLC and not found in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore prefetch code reads satisfied by the LLC and HIT in a sibling core", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x240", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x240", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch code reads satisfied by the LLC and HIT in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore prefetch code reads satisfied by the LLC and HITM in a sibling core", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x440", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x440", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch code reads satisfied by the LLC and HITM in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore prefetch code reads satisfied by the LLC", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x740", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x740", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch code reads satisfied by the LLC", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore prefetch code reads satisfied by the LLC or local DRAM", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2740", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2740", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch code reads satisfied by the LLC or local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore prefetch code reads satisfied by a remote cache", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1840", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1840", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch code reads satisfied by a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore prefetch code reads satisfied by a remote cache or remote DRAM", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x5840", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x5840", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch code reads satisfied by a remote cache or remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore prefetch code reads that HIT in a remote cache", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1040", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1040", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch code reads that HIT in a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore prefetch code reads that HITM in a remote cache", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x840", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x840", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch code reads that HITM in a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore prefetch RFO requests satisfied by any cache or DRAM.", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x7F20", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x7F20", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch RFO requests satisfied by any cache or DRAM.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "All offcore prefetch RFO requests", "EventCode": "0xB7, 0xBB", - "MSRValue": "0xFF20", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xFF20", "SampleAfterValue": "100000", - "BriefDescription": "All offcore prefetch RFO requests", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore prefetch RFO requests satisfied by the IO, CSR, MMIO unit", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x8020", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.PF_RFO.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8020", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch RFO requests satisfied by the IO, CSR, MMIO unit", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and not found in a sibling core", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x120", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x120", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and not found in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and HIT in a sibling core", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x220", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x220", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and HIT in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and HITM in a sibling core", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x420", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x420", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and HITM in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x720", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x720", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC or local DRAM", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2720", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2720", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC or local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore prefetch RFO requests satisfied by a remote cache", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1820", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1820", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch RFO requests satisfied by a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore prefetch RFO requests satisfied by a remote cache or remote DRAM", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x5820", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x5820", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch RFO requests satisfied by a remote cache or remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore prefetch RFO requests that HIT in a remote cache", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1020", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1020", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch RFO requests that HIT in a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore prefetch RFO requests that HITM in a remote cache", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x820", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x820", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch RFO requests that HITM in a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore prefetch requests satisfied by any cache or DRAM.", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x7F70", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x7F70", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch requests satisfied by any cache or DRAM.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "All offcore prefetch requests", "EventCode": "0xB7, 0xBB", - "MSRValue": "0xFF70", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xFF70", "SampleAfterValue": "100000", - "BriefDescription": "All offcore prefetch requests", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore prefetch requests satisfied by the IO, CSR, MMIO unit", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x8070", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.PREFETCH.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8070", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch requests satisfied by the IO, CSR, MMIO unit", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore prefetch requests satisfied by the LLC and not found in a sibling core", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x170", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x170", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch requests satisfied by the LLC and not found in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore prefetch requests satisfied by the LLC and HIT in a sibling core", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x270", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x270", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch requests satisfied by the LLC and HIT in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore prefetch requests satisfied by the LLC and HITM in a sibling core", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x470", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x470", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch requests satisfied by the LLC and HITM in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore prefetch requests satisfied by the LLC", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x770", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x770", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch requests satisfied by the LLC", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore prefetch requests satisfied by the LLC or local DRAM", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2770", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2770", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch requests satisfied by the LLC or local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore prefetch requests satisfied by a remote cache", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1870", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1870", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch requests satisfied by a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore prefetch requests satisfied by a remote cache or remote DRAM", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x5870", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x5870", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch requests satisfied by a remote cache or remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore prefetch requests that HIT in a remote cache", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1070", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1070", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch requests that HIT in a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Offcore prefetch requests that HITM in a remote cache", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x870", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x870", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch requests that HITM in a remote cache", - "Offcore": "1" + "UMask": "0x1" + }, + { + "BriefDescription": "Super Queue LRU hints sent to LLC", + "EventCode": "0xF4", + "EventName": "SQ_MISC.LRU_HINTS", + "SampleAfterValue": "2000000", + "UMask": "0x4" + }, + { + "BriefDescription": "Super Queue lock splits across a cache line", + "EventCode": "0xF4", + "EventName": "SQ_MISC.SPLIT_LOCK", + "SampleAfterValue": "2000000", + "UMask": "0x10" + }, + { + "BriefDescription": "Loads delayed with at-Retirement block code", + "EventCode": "0x6", + "EventName": "STORE_BLOCKS.AT_RET", + "SampleAfterValue": "200000", + "UMask": "0x4" + }, + { + "BriefDescription": "Cacheable loads delayed with L1D block code", + "EventCode": "0x6", + "EventName": "STORE_BLOCKS.L1D_BLOCK", + "SampleAfterValue": "200000", + "UMask": "0x8" } -]
\ No newline at end of file +] |