aboutsummaryrefslogtreecommitdiffstatshomepage
AgeCommit message (Collapse)AuthorFilesLines
2023-06-15arm64: dts: ti: Unify pin group node names for make dtbs checksTony Lindgren31-409/+409
Prepare for pinctrl-single yaml binding and unify pin group node names. Let's standardize on pin group node naming ending in -pins. As we don't necessarily have a SoC specific compatible property for pinctrl-single. I'd rather not add a pattern match for pins somewhere in the name for all the users. Trying to add matches for pins-default will be futile as on the earlier SoCs we've already seen names like pins-sleep, pins-idle, pins-off and so on that would need to be matched. And as the node is a pin group, let's prefer to use naming -pins rather than -pin as more pins may need to be added to the pin group later on. Signed-off-by: Tony Lindgren <tony@atomide.com> [vigneshr@ti.com: Rebase onto latest ti/next and extend to new nodes] Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2023-06-15arm64: dts: ti: add verdin am62 yaviaFrancesco Dolcini4-0/+253
Add Toradex Verdin AM62 Yavia. Link: https://www.toradex.com/products/carrier-board/yavia Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com> Link: https://lore.kernel.org/r/20230615095058.33890-6-francesco@dolcini.it Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2023-06-15arm64: dts: ti: add verdin am62 dahliaFrancesco Dolcini4-0/+207
Add Toradex Verdin AM62 Dahlia. Link: https://www.toradex.com/products/carrier-board/dahlia-carrier-board-kit Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com> Link: https://lore.kernel.org/r/20230615095058.33890-5-francesco@dolcini.it Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2023-06-15arm64: dts: ti: add verdin am62Francesco Dolcini7-0/+1696
This patch adds the device tree to support Toradex Verdin AM62 a computer on module which can be used on different carrier boards and the Toradex Verdin Development Board carrier board. The module consists of an TI AM62 family SoC (either AM623 or AM625), a TPS65219 PMIC, a Gigabit Ethernet PHY, 512MB to 2GB of LPDDR4 RAM, an eMMC, a TLA2024 ADC, an I2C EEPROM, an RX8130 RTC, and optional Parallel RGB to MIPI DSI bridge plus an optional Bluetooth/Wi-Fi module. Anything that is not self-contained on the module is disabled by default. So far there is no display nor USB role switch supported, apart of that all the other functionalities are fine. Link: https://developer.toradex.com/hardware/verdin-som-family/modules/verdin-am62/ Link: https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62 Link: https://www.toradex.com/products/carrier-board/verdin-development-board-kit Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com> Link: https://lore.kernel.org/r/20230615095058.33890-4-francesco@dolcini.it Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2023-06-15dt-bindings: arm: ti: add toradex,verdin-am62 et al.Francesco Dolcini1-0/+20
Add toradex,verdin-am62 for Toradex Verdin AM62 SoM, its nonwifi and wifi variants and the carrier boards (Dahlia, Verdin Development Board and Yavia) they may be mated in. Link: https://developer.toradex.com/hardware/verdin-som-family/modules/verdin-am62/ Link: https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62 Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20230615095058.33890-2-francesco@dolcini.it Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2023-06-15arm64: dts: ti: Add basic support for phyBOARD-Lyra-AM625Wadim Egorov3-0/+591
The phyCORE-AM62x [1] is a SoM (System on Module) featuring TI's AM62x SoC. It can be used in combination with different carrier boards. This module can come with different sizes and models for DDR, eMMC, SPI NOR Flash and various SoCs from the AM62x family. A development Kit, called phyBOARD-Lyra [2] is used as a carrier board reference design around the AM62x SoM. Supported features: * Debug UART * SPI NOR Flash * eMMC * 2x Ethernet * Micro SD card * I2C EEPROM * I2C RTC * GPIO Expander * LEDs * USB For more details, see: [1] Product page SoM: https://www.phytec.com/product/phycore-am62x [2] Product page CB: https://www.phytec.com/product/phyboard-am62x Signed-off-by: Wadim Egorov <w.egorov@phytec.de> Reviewed-by: Tony Lindgren <tony@atomide.com> Link: https://lore.kernel.org/r/20230504140143.1425951-2-w.egorov@phytec.de Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2023-06-15dt-bindings: arm: ti: Add bindings for PHYTEC AM62x based hardwareWadim Egorov1-0/+6
Add devicetree bindings for AM62x based phyCORE-AM62 SoM and phyBOARD-Lyra RDK. Signed-off-by: Wadim Egorov <w.egorov@phytec.de> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Tony Lindgren <tony@atomide.com> Link: https://lore.kernel.org/r/20230504140143.1425951-1-w.egorov@phytec.de Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2023-06-15arm64: dts: ti: k3-j7200-mcu-wakeup: Remove 0x unit address prefix from nodenameNishanth Menon1-3/+3
unit-address should not use a 0x prefix. Signed-off-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20230424173623.477577-2-nm@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2023-06-15arm64: dts: ti: k3-j721e-som-p0: Enable wakeup_i2c0 and eepromNishanth Menon1-0/+13
Enable wakeup_i2c and use un-used pinmux. While at it, describe the board detection eeprom present on the board. Signed-off-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20230601183151.1000157-6-nm@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2023-06-15arm64: dts: ti: k3-am64: Add ESM supportNishanth Menon2-0/+12
Add Error Signaling Module (ESM) instances in MCU and MAIN domains. Signed-off-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20230530185335.79942-3-nm@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2023-06-15arm64: dts: ti: k3-am62: Add ESM supportNishanth Menon2-0/+12
Add Error Signaling Module (ESM) instances in MCU and MAIN domains. Signed-off-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20230530185335.79942-2-nm@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2023-06-15arm64: dts: ti: k3-j7200: Add ESM supportNeha Malcom Francis2-0/+7
Add address entry mapping ESM on J7200. Signed-off-by: Neha Malcom Francis <n-francis@ti.com> Link: https://lore.kernel.org/r/20230504080526.133149-4-n-francis@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2023-06-15arm64: dts: ti: k3-j721e: Add ESM supportNeha Malcom Francis2-0/+7
Add address entry mapping ESM on J721E. Signed-off-by: Neha Malcom Francis <n-francis@ti.com> Link: https://lore.kernel.org/r/20230504080526.133149-3-n-francis@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2023-06-15dt-bindings: misc: esm: Add ESM support for TI K3 devicesNeha Malcom Francis1-0/+53
Document the binding for TI K3 ESM (Error Signaling Module) block. Signed-off-by: Neha Malcom Francis <n-francis@ti.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20230504080526.133149-2-n-francis@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2023-06-15arm64: dts: ti: k3-j721s2-som-p0: Enable wakeup_i2c0 and eepromNishanth Menon1-0/+22
Enable wakeup_i2c and use un-used pinmux. While at it, describe the board detection eeprom present on the board. Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Udit Kumar <u-kumar1@ti.com> Link: https://lore.kernel.org/r/20230602153554.1571128-7-nm@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2023-06-15arm64: dts: ti: k3-j721s2-common-proc-board: Add uart pinmuxNishanth Menon1-1/+22
Define the wakeup uart pin-mux for completeness and add explicit muxing for mcu_uart0. This allows the device tree usage in bootloader and firmwares that can configure the same appropriately. Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Udit Kumar <u-kumar1@ti.com> Link: https://lore.kernel.org/r/20230602153554.1571128-6-nm@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2023-06-15arm64: dts: ti: k3-am68-sk-som: Enable wakeup_i2c0 and eepromNishanth Menon1-0/+22
Enable wakeup_i2c. While at it, describe the board detection eeprom present on the board. Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Sinthu Raja <sinthu.raja@ti.com> Reviewed-by: Udit Kumar <u-kumar1@ti.com> Link: https://lore.kernel.org/r/20230602153554.1571128-5-nm@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2023-06-15arm64: dts: ti: k3-am68-sk-base-board: Add uart pinmuxNishanth Menon1-0/+26
Define the wakeup uart pin-mux for completeness and add explicit muxing for mcu_uart0. This allows the device tree usage in bootloader and firmwares that can configure the same appropriately. Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Udit Kumar <u-kumar1@ti.com> Link: https://lore.kernel.org/r/20230602153554.1571128-4-nm@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2023-06-15arm64: dts: ti: k3-am68-sk-base-board: Add pinmux for RPi HeaderSinthu Raja1-1/+76
Add pinmux required to bring out the i2c and gpios on 40-pin RPi expansion header on the AM68 SK board. Signed-off-by: Sinthu Raja <sinthu.raja@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Udit Kumar <u-kumar1@ti.com> Link: https://lore.kernel.org/r/20230602153554.1571128-3-nm@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2023-06-15arm64: dts: ti: k3-j721s2: Fix wkup pinmux rangeSinthu Raja3-60/+87
The WKUP_PADCONFIG register region in J721S2 has multiple non-addressable regions, accordingly split the existing wkup_pmx region as follows to avoid the non-addressable regions and include the rest of valid WKUP_PADCONFIG registers. Also update references to old nodes with new ones. wkup_pmx0 -> 13 pins (WKUP_PADCONFIG 0 - 12) wkup_pmx1 -> 11 pins (WKUP_PADCONFIG 14 - 24) wkup_pmx2 -> 72 pins (WKUP_PADCONFIG 26 - 97) wkup_pmx3 -> 1 pin (WKUP_PADCONFIG 100) Fixes: b8545f9d3a54 ("arm64: dts: ti: Add initial support for J721S2 SoC") Cc: <stable@vger.kernel.org> # 6.3 Signed-off-by: Sinthu Raja <sinthu.raja@ti.com> Signed-off-by: Thejasvi Konduru <t-konduru@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Udit Kumar <u-kumar1@ti.com> Link: https://lore.kernel.org/r/20230602153554.1571128-2-nm@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2023-06-15arm64: dts: ti: k3-j7200: Drop SoC level aliasesUdit Kumar1-17/+0
Aiases are defined at board level, so dropping from soc level Signed-off-by: Udit Kumar <u-kumar1@ti.com> Reviewed-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20230611111140.3189111-7-u-kumar1@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2023-06-15arm64: dts: ti: k3-j7200-common-proc-board: Define aliases at board levelUdit Kumar1-0/+10
Define aliases at board level Signed-off-by: Udit Kumar <u-kumar1@ti.com> Reviewed-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20230611111140.3189111-6-u-kumar1@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2023-06-15arm64: dts: ti: k3-j7200-common-proc-board: Add uart pinmuxUdit Kumar1-1/+57
Add main, mcu, wakeup domain uart0 pin mux into common board file and it's reference to uart node. Signed-off-by: Udit Kumar <u-kumar1@ti.com> Reviewed-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20230611111140.3189111-5-u-kumar1@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2023-06-15arm64: dts: ti: k3-j7200-common-proc-board: remove duplicate main_i2c0 pin muxUdit Kumar1-7/+0
main_i2c0 pin mux was duplicated in som and common file. So removing duplicated node from common file. Signed-off-by: Udit Kumar <u-kumar1@ti.com> Reviewed-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20230611111140.3189111-4-u-kumar1@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2023-06-15arm64: dts: ti: k3-j7200: Configure pinctrl for timer IO padsUdit Kumar2-0/+38
There are timer IO pads in the MCU domain, and in the MAIN domain. These pads can be muxed for the related timers. There are timer IO control registers for input and output. The registers for CTRLMMR_TIMER*_CTRL and CTRLMMR_MCU_TIMER*_CTRL are used to control the input. The registers for CTCTRLMMR_TIMERIO*_CTRL and CTRLMMR_MCU_TIMERIO*_CTRL the output. The multiplexing is documented in TRM "5.1.2.3.1.4 Timer IO Muxing Control Registers" and "5.1.3.3.1.5 Timer IO Muxing Control Registers", and the CASCADE_EN bit is documented in TRM "12.6.3.1 Timers Overview". For chaining timers, the timer IO control registers also have a CASCADE_EN input bit in the CTRLMMR_TIMER*_CTRL in the registers. The CASCADE_EN bit muxes the previous timer output, or possibly and external TIMER_IO pad source, to the input clock of the selected timer instance for odd numered timers. For the even numbered timers, the CASCADE_EN bit does not do anything. The timer cascade input routing options are shown in TRM "Figure 12-3224. Timers Overview". For handling beyond multiplexing, the driver support for timer cascading should be likely be handled via the clock framework. The MCU timer controls are also marked as reserved for usage by the MCU firmware. Cc: Nishanth Menon <nm@ti.com> Cc: Vignesh Raghavendra <vigneshr@ti.com> Cc: Tony Lindgren <tony@atomide.com> Reviewed-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Udit Kumar <u-kumar1@ti.com> Reviewed-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20230611111140.3189111-3-u-kumar1@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2023-06-15arm64: dts: ti: k3-j7200: Add general purpose timersUdit Kumar2-0/+370
There are 20 general purpose timers on j721e that can be used for things like PWM using pwm-omap-dmtimer driver. There are also additional ten timers in the MCU domain which are meant for MCU firmware usage and hence marked reserved by default. The odd numbered timers have the option of being cascaded to even timers to create a 64 bit non-atomic counter which is racy in simple usage, hence the clock muxes are explicitly setup to individual 32 bit counters driven off system crystal (HFOSC) as default. Signed-off-by: Udit Kumar <u-kumar1@ti.com> Reviewed-by: Tony Lindgren <tony@atomide.com> Reviewed-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20230611111140.3189111-2-u-kumar1@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2023-06-15arm64: dts: ti: k3-j721e: Drop SoC level aliasesNishanth Menon1-19/+0
Drop the SoC level aliases as these need to be done at board level. Signed-off-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20230601183151.1000157-10-nm@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2023-06-15arm64: dts: ti: k3-j721e-common-proc-board: Define aliases at board levelNishanth Menon1-0/+12
Define the aliases at the board level instead of using generic aliases at SoC level. Signed-off-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20230601183151.1000157-9-nm@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2023-06-15arm64: dts: ti: k3-j721e-sk: Define aliases at board levelNishanth Menon1-0/+9
Define the aliases at the board level instead of using generic aliases at SoC level. Signed-off-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20230601183151.1000157-8-nm@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2023-06-15arm64: dts: ti: k3-j721e-beagleboneai64: Add wakeup_uart pinmuxNishanth Menon1-0/+10
Define the wakeup uart pin-mux for completeness. This allows the device tree usage in bootloader and firmwares that can configure the same appropriately. Signed-off-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20230601183151.1000157-7-nm@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2023-06-15arm64: dts: ti: k3-j721e-som-p0: Enable wakeup_i2c0 and eepromNishanth Menon1-0/+13
Enable wakeup_i2c and use un-used pinmux. While at it, describe the board detection eeprom present on the board. Signed-off-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20230601183151.1000157-6-nm@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2023-06-15arm64: dts: ti: j721e-common-proc-board: Add uart pinmuxNishanth Menon1-4/+58
Explicitly define the pinmux rather than depend on bootloader configured pinmux for the platform. Signed-off-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20230601183151.1000157-5-nm@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2023-06-15arm64: dts: ti: j721e-som/common-proc-board: Add product linksNishanth Menon2-0/+4
Add product links to get reference to schematics and design files Signed-off-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20230601183151.1000157-4-nm@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2023-06-15arm64: dts: ti: k3-j721e-sk: Enable wakeup_i2c0 and eepromNishanth Menon1-0/+13
Enable wakeup_i2c and use un-used pinmux. While at it, describe the board detection eeprom present on the board. Signed-off-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20230601183151.1000157-3-nm@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2023-06-15arm64: dts: ti: k3-j721e-sk: Add missing uart pinmuxesNishanth Menon1-2/+29
Rather than depend on the default pinmuxes, explicitly describe the pinmux Signed-off-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20230601183151.1000157-2-nm@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2023-06-15arm64: dts: ti: k3-am64: Use phandle to stdout UART nodeAndrew Davis2-2/+2
Using a phandle makes it clear which UART we are choosing without needing to resolve through an alias first. Especially useful for boards like the TI J721s2-EVM where the alias is "serial2" but it actually resolves to the 8th UART instance(main_uart8). Signed-off-by: Andrew Davis <afd@ti.com> Link: https://lore.kernel.org/r/20230601184933.358731-2-afd@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2023-06-15arm64: dts: ti: k3-am64: Only set UART baud for used portsAndrew Davis5-9/+4
As the binding for "current-speed" states, this should only be used when the baud rate of an attached device cannot be detected. This is the case for our attached on-board USB-to-UART converter used for early kernel console. For all other unconnected/disabled ports this can be configured in userspace later, DT is not the place for device configuration, especially when there are already standard ways to set serial baud in userspace. Remove setting baud for all disabled serial ports and move setting it for the couple enabled ports down into the board files. Signed-off-by: Andrew Davis <afd@ti.com> Link: https://lore.kernel.org/r/20230601184933.358731-1-afd@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2023-06-15arm64: dts: ti: k3-am69-sk: Add pinmux for RPi HeaderDasnavis Sabiya1-0/+63
Add pinmux required to bring out the i2c and gpios on 40 pin RPi expansion header on AM69 SK board. Signed-off-by: Dasnavis Sabiya <sabiya.d@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Udit Kumar <u-kumar1@ti.com> Link: https://lore.kernel.org/r/20230602214937.2349545-9-nm@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2023-06-15arm64: dts: ti: k3-am69-sk: Enable wakeup_i2c0 and eepromNishanth Menon1-0/+21
Enable wakeup_i2c and use un-used pinmux. While at it, describe the board detection eeprom present on the board. Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Udit Kumar <u-kumar1@ti.com> Link: https://lore.kernel.org/r/20230602214937.2349545-8-nm@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2023-06-15arm64: dts: ti: k3-am69-sk: Add mcu and wakeup uartsNishanth Menon1-0/+31
Add wakeup and MCU uart. This allows the device tree usage in bootloader and firmwares that can configure the same appropriately. Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Udit Kumar <u-kumar1@ti.com> Link: https://lore.kernel.org/r/20230602214937.2349545-7-nm@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2023-06-15arm64: dts: ti: k3-am69-sk: Enable mcu network portNishanth Menon1-0/+48
Enable networking for NFS and basic networking functionality. Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Udit Kumar <u-kumar1@ti.com> Link: https://lore.kernel.org/r/20230602214937.2349545-6-nm@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2023-06-15arm64: dts: ti: k3-am69-sk: Fix main_i2c0 aliasNishanth Menon1-1/+1
main_i2c0 is aliased as i2c0 which creates a problem for u-boot R5 SPL attempting to reuse the same definition in the common board detection logic as it looks for the first i2c instance as the bus on which to detect the eeprom to understand the board variant involved. Switch main_i2c0 to i2c3 alias allowing us to introduce wkup_i2c0 and potentially space for mcu_i2c instances in the gap for follow on patches. Fixes: 635fb18ba008 ("arch: arm64: dts: Add support for AM69 Starter Kit") Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Udit Kumar <u-kumar1@ti.com> Link: https://lore.kernel.org/r/20230602214937.2349545-5-nm@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2023-06-15arm64: dts: ti: k3-j784s4-evm: Enable wakeup_i2c0 and eepromNishanth Menon1-0/+21
Enable wakeup_i2c and use un-used pinmux. While at it, describe the board detection eeprom present on the board. Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Udit Kumar <u-kumar1@ti.com> Link: https://lore.kernel.org/r/20230602214937.2349545-4-nm@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2023-06-15arm64: dts: ti: k3-j784s4-evm: Add mcu and wakeup uartsNishanth Menon1-0/+33
Add wakeup and MCU uart. This allows the device tree usage in bootloader and firmwares that can configure the same appropriately. Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Udit Kumar <u-kumar1@ti.com> Link: https://lore.kernel.org/r/20230602214937.2349545-3-nm@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2023-06-15arm64: dts: ti: k3-j784s4: Fix wakeup pinmux range and pinctrl node offsetsThejasvi Konduru2-16/+43
The wkup_pmx register region in j784s4 has multiple non-addressable regions, hence the existing wkup_pmx region is split as follows to avoid the non-addressable regions. The pinctrl node offsets are also corrected as per the newly split wkup_pmx* nodes. wkup_pmx0 -> 13 pins (WKUP_PADCONFIG 0 - 12) wkup_pmx1 -> 11 pins (WKUP_PADCONFIG 14 - 24) wkup_pmx2 -> 72 pins (WKUP_PADCONFIG 26 - 97) wkup_pmx3 -> 1 pin (WKUP_PADCONFIG 100) Fixes: 4664ebd8346a ("arm64: dts: ti: Add initial support for J784S4 SoC") Signed-off-by: Thejasvi Konduru <t-konduru@ti.com> Reviewed-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20230503083143.32369-1-t-konduru@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2023-06-15arm64: dts: ti: k3-j784s4-evm: Fix main_i2c0 aliasNishanth Menon1-1/+1
main_i2c0 is aliased as i2c0 which creates a problem for u-boot R5 SPL attempting to reuse the same definition in the common board detection logic as it looks for the first i2c instance as the bus on which to detect the eeprom to understand the board variant involved. Switch main_i2c0 to i2c3 alias allowing us to introduce wkup_i2c0 and potentially space for mcu_i2c instances in the gap for follow on patches. Fixes: e20a06aca5c9 ("arm64: dts: ti: Add support for J784S4 EVM board") Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Udit Kumar <u-kumar1@ti.com> Link: https://lore.kernel.org/r/20230602214937.2349545-2-nm@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2023-06-15arm64: dts: ti: k3-j721s2: Change CPTS clock parentNeha Malcom Francis2-0/+4
MAIN_PLL0 has a flag set in DM (Device Manager) that removes it's capability to re-initialise clock frequencies. CPTS and RGMII has MAIN_PLL3 as their parent which does not have this flag. While RGMII needs this reinitialisation to default frequency to be able to get 250MHz with its divider, CPTS can not get its required 200MHz with its divider. Thus, move CPTS clock parent on J721S2 from MAIN_PLL3_HSDIV1 to MAIN_PLL0_HSDIV6. (Note: even GTC will be moved from MAIN_PLL3 to MAIN_PLL0 in U-Boot side for the same reason) Signed-off-by: Neha Malcom Francis <n-francis@ti.com> Link: https://lore.kernel.org/r/20230605110443.84568-1-n-francis@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2023-06-15arm64: dts: ti: k3-am69-sk: Add eMMC mmc0 supportDasnavis Sabiya1-0/+9
Add support for eMMC card connected to main sdhci0 instance. Signed-off-by: Dasnavis Sabiya <sabiya.d@ti.com> Reviewed-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20230605174551.160262-1-sabiya.d@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2023-06-15arm64: dts: ti: k3-am68-sk-base-board: Fixup reference to phandles arrayNishanth Menon1-1/+1
When referring to array of phandles, using <> to separate the array entries is better notation as it makes potential errors with phandle and cell arguments easier to catch. Fix the outliers to be consistent with the rest of the usage. Signed-off-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20230606182220.3661956-15-nm@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2023-06-15arm64: dts: ti: k3-am654-base-board: Fixup reference to phandles arrayNishanth Menon1-2/+2
When referring to array of phandles, using <> to separate the array entries is better notation as it makes potential errors with phandle and cell arguments easier to catch. Fix the outliers to be consistent with the rest of the usage. Signed-off-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20230606182220.3661956-14-nm@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Copyright © 1996 – 2023 Jason A. Donenfeld. All Rights Reverse Engineered.