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2026-07-29ASoC: sunxi: sun4i-codec: Use dev_err_probe() for probe error handlingbui duc phuc1-42/+28
Use dev_err_probe() for probe error handling to simplify the error paths and handle -EPROBE_DEFER correctly. Signed-off-by: bui duc phuc <phucduc.bui@gmail.com> Link: https://patch.msgid.link/20260715095525.40668-2-phucduc.bui@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org>
2026-07-29ovpn: add missing rtnl_link_ops->get_size callbackRalf Lici1-0/+7
ovpn_fill_info emits IFLA_OVPN_MODE inside IFLA_INFO_DATA, but ovpn_link_ops does not provide a get_size callback. Consequently, rtnetlink's size estimate for ovpn link messages does not include the nested mode attribute. Available skb tailroom may hide this mismatch. When the remaining space is insufficient, however, ovpn_fill_info returns -EMSGSIZE and message construction fails. Add the callback and account for IFLA_OVPN_MODE. Fixes: c2d950c4672a ("ovpn: add basic interface creation/destruction/management routines") Signed-off-by: Ralf Lici <ralf@mandelbit.com> Signed-off-by: Antonio Quartulli <antonio@openvpn.net>
2026-07-29powerpc: Move CONFIG_QE_GPIO to SoCChristophe Leroy (CS GROUP)3-8/+9
Commit 7aa1aa6ecec2 ("QE: Move QE from arch/powerpc to drivers/soc") moved QE into drivers/soc including gpio.c but left CONFIG_QE_GPIO in powerpc's Kconfig. Move it to SoC as well as it is the only place it is used: drivers/soc/fsl/qe/Makefile:obj-$(CONFIG_QE_GPIO) += gpio.o qe_ports_ic.o include/soc/fsl/qe/qe.h:#ifdef CONFIG_QE_GPIO include/soc/fsl/qe/qe.h:#endif /* CONFIG_QE_GPIO */ There is also a dependency in USB subsystem for CONFIG_USB_FHCI_HCD: drivers/usb/host/Kconfig: depends on QE_GPIO && QUICC_ENGINE Because that USB driver selects CONFIG_FSL_GTM which is specific to powerpc, it has to depend on CONFIG_PPC. Acked-by: Madhavan Srinivasan <maddy@linux.ibm.com> Link: https://lore.kernel.org/r/9a7131d15a94e2017877e628f0e97f9aa2e0aae9.1785140877.git.chleroy@kernel.org Signed-off-by: Christophe Leroy (CS GROUP) <chleroy@kernel.org>
2026-07-29fprobe: Fix module reference count leak on error in register_fprobe()Masami Hiramatsu (Google)1-4/+2
In register_fprobe(), get_ips_from_filter() resolves target function addresses and increments module reference counts via try_module_get() for symbols in kernel modules. If get_ips_from_filter() fails on the second pass and returns an error, register_fprobe() returned directly without releasing module references acquired up to that point. Fix this by ensuring the cleanup loop executing module_put() runs even when get_ips_from_filter() returns a negative error. Link: https://lore.kernel.org/all/178528125360.101985.4144133640239273153.stgit@devnote2/ Fixes: d24fa977eec5 ("tracing: fprobe: Fix to lock module while registering fprobe") Assisted-by: Antigravity:gemini-3.6-flash Signed-off-by: Masami Hiramatsu (Google) <mhiramat@kernel.org>
2026-07-29drm/xe/pt: check no-DMA huge-pte cases before DMA segment testHimal Prasad Ghimiray1-5/+8
On a non-range clear, curs.size is never set, so the segment test (next - va_curs_start > curs->size) returns false for every level > 0 before the clear_pt short-circuit is reached. The clear then descends to level 0 instead of forming a huge zero-leaf, wasting page tables and risking -ENOMEM on unbind. Move the null-VMA, purged-BO and clear_pt short-circuits above the curs->size test. The bind path always sets curs.size, so it is unaffected. v2 - Also set curs.size on the clear path so the cursor stays meaningful during the walk. clear_pt is only reached with range == NULL, so assert that invariant. (Matthew Brost) Cc: Matthew Brost <matthew.brost@intel.com> Fixes: 5b658b7e89c3 ("drm/xe: Clear scratch page on vm_bind") Reported-by: Sashiko <sashiko-bot@kernel.org> Reviewed-by: Matthew Brost <matthew.brost@intel.com> Link: https://patch.msgid.link/20260728055916.593707-2-himal.prasad.ghimiray@intel.com Signed-off-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com> (cherry picked from commit 04eeeb45cb61b8a3e9d785003457e550c920ba49) Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2026-07-29ASoC: dt-bindings: realtek,rt5640: Make interrupts optionalFabio Estevam1-1/+0
The RT5640 GPIO1/IRQ pin can be configured either as GPIO1 or as the codec interrupt output. Some boards, such as the Firefly-RK3399, do not connect the codec interrupt output. This causes the following binding validation warning: 'interrupts' is a required property Make the interrupts property optional to support such hardware configurations. Signed-off-by: Fabio Estevam <festevam@gmail.com> Link: https://patch.msgid.link/20260727185814.2599488-1-festevam@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org>
2026-07-29drm/imagination: Update the trace point pvr_job_submit_fw()Brajesh Gupta1-2/+5
Trace point pvr_job_submit_fw() is used to trace job submission to the FW. Currently it is recorded when a command is written to the Client circular buffer. Move trace recording after writing command to the Kernel circular buffer to better represent command submission to the FW. Fixes: c1079aebb4de ("drm/imagination: Add support for trace points") Signed-off-by: Brajesh Gupta <brajesh.gupta@imgtec.com> Reviewed-by: Alessio Belle <alessio.belle@imgtec.com> Link: https://patch.msgid.link/20260724-b4-tracepoint-fix-v3-1-8f8e5e8179d3@imgtec.com Signed-off-by: Alessio Belle <alessio.belle@imgtec.com>
2026-07-29Merge tag 'socfpga_dts_updates_for_v7.3' of https://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into soc/dtArnd Bergmann12-14/+346
SoCFPGA DTS updates for v7.3 - dt-bindings updates: - Document compatible for Agilex72 - Document additional interrupts for Agilex5 - Add the additional interrupts for the gmac on Agilex5 - Use decimal number for interrupts, not hexadecimal - Enable the SMMU on Agilex5 - Add dma-coherent on XGMAC nodes - Add initial support for the Agilex72 SoCDK - Correct indentation on Arria10 - Update QSPI boot partition label * tag 'socfpga_dts_updates_for_v7.3' of https://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux: arm64: dts: socfpga: use consistent QSPI boot partition label ARM: dts: intel: arria10: Correct indentation arm64: dts: socfpga: agilex5: update channel interrupts for gmac1 and gmac2 dt-bindings: net: altr,socfpga-stmmac: add more interrupts for Agilex5 arm64: dts: socfpga: agilex72: Add initial device tree dt-bindings: arm: altera: Add Agilex72 SoCFPGA compatible strings arm64: dts: socfpga: agilex5: Add dma-coherent to XGMAC nodes arm64: dts: socfpga: agilex5: Enable the SMMU arm64: dts: intel: keembay: Always use decimal interrupts arm64: dts: socfpga: agilex5: Add per-channel interrupts to gmac0 Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2026-07-29Merge tag 'v7.3-rockchip-dts32-1' of https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into soc/dtArnd Bergmann8-0/+587
New board: Alientek DLRV1126 Eeprom for RK3288-Tinker-board * tag 'v7.3-rockchip-dts32-1' of https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: ARM: dts: rockchip: Add Alientek DLRV1126 ARM: dts: rockchip: Add RV1126 I2C5 dt-bindings: arm: rockchip: Add Alientek DLRV1126 dt-bindings: vendor-prefixes: add alientek ARM: dts: rockchip: add eeprom node to rk3288-tinker Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2026-07-29fsnotify: Remove Matt Bobrowski as a reviewerJan Kara1-1/+0
Matt was not very active reviewer in last years. Furthermore he apparently left Google and his email doesn't work anymore. I didn't find any working contact for him so at least for now delete the entry with non-existent email. Signed-off-by: Jan Kara <jack@suse.cz>
2026-07-29Merge tag 'thead-dt-for-v7.3' of https://git.kernel.org/pub/scm/linux/kernel/git/fustini/linux into soc/dtArnd Bergmann2-37/+157
T-HEAD device tree changes for v7.3 There is just one set of changes that the remaining IO expansion chips on the TH1520-based LicheePi 4a board. * tag 'thead-dt-for-v7.3' of https://git.kernel.org/pub/scm/linux/kernel/git/fustini/linux: riscv: dts: thead: Add remaining Lichee Pi 4A IO expansions riscv: dts: thead: Add IO labels for the IO expansion on I2C1 riscv: dts: thead: lpi4a: sort nodes riscv: dts: thead: Add TH1520 I2C nodes riscv: dts: thead: th1520: remove pclk for I2C1 Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2026-07-29drm/i915/dp: Ignore the sink's DSC max FRL rate without a PCON DSC encoderAlexander Kaplan1-1/+8
intel_dp_hdmi_sink_max_frl() limits the sink's max FRL rate by its DSC max FRL rate whenever the sink supports DSC 1.2. However, the DSC max FRL rate (HF-VSDB DSC_Max_FRL_Rate) only applies to compressed video transport, which requires a DSC 1.2 encoder in the PCON (configured via intel_dp_pcon_dsc_configure()). Without such an encoder the HDMI link always carries uncompressed video, for which the regular Max_FRL_Rate is the correct limit. Applying the DSC limit unconditionally trains the FRL link at a lower rate than both the PCON and the sink support. E.g. an LG OLED G4 (Max_FRL_Rate 48 Gbps, DSC_Max_FRL_Rate 24 Gbps) behind a Synaptics VMM7100 PCON (PCON max FRL bw 48 Gbps, no DSC encoder): Sink max rate from EDID = 24 Gbps FRL trained with : 24 Gbps while Windows/macOS train the same hardware at 40/48 Gbps. The too low FRL rate needlessly constrains the formats available to the sink. Only apply the sink's DSC max FRL rate if the PCON has a DSC 1.2 encoder, matching the gate in intel_dp_pcon_dsc_configure(). PCONs with a DSC encoder keep the current conservative behavior, since the link is trained once and compressed transport may be used for any subsequent mode. With this the setup above trains at 48 Gbps. Tested on PTL (xe) with the above PCON/sink combo. Fixes: 10fec80b48c5 ("drm/i915/display: Configure PCON for DSC1.1 to DSC1.2 encoding") Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Signed-off-by: Alexander Kaplan <alexander.kaplan@sms-medipool.de> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Link: https://patch.msgid.link/20260718105207.5565-3-alexander.kaplan@sms-medipool.de (cherry picked from commit 71b57dd92f94569dca4bdf883fbd8ca5d4ed4bae) Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2026-07-29Merge tag 'samsung-dt64-7.3' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into soc/dtArnd Bergmann7-0/+829
Samsung DTS ARM64 changes for v7.3 1. New SoC Exynos8855 (market naming: Exynos 1580) basic support with its SMDK development board. That's a 8-core SoC, released in Q4 2024. 2. ExynosAutov920: Add HSI0 syscon node. * tag 'samsung-dt64-7.3' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: MAINTAINERS: Add entry for Samsung Exynos8855 SoC arm64: dts: exynos: add initial support for Samsung Exynos8855 smdk dt-binding: ARM: samsung: Add Samsung Exynos8855 arm64: dts: exynosautov920: Add hsi0 syscon node for PCIe PHY Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2026-07-29ext2: Simplify error handling of IO error when adding xattrJan Kara1-9/+5
When we fail to write out inode when adding new xattr block, we backed out some changes (like quota modifications) but left others (like block allocation or inode xattr block modification). Just leave the inode intact in this case because we can hardly reach a consistent state and defer fixing to e2fsck. Also remove outdated comment and special data handling since sync_inode_metadata() does not write out any data. Link: https://patch.msgid.link/20260728154724.3934977-2-jack@suse.cz Signed-off-by: Jan Kara <jack@suse.cz>
2026-07-29KVM: riscv: selftests: add Zicfiss/Zicfilp extension to get-reg-list testInochi Amaoto1-0/+69
The KVM RISC-V allows Zicfiss/Zicfilp extensions for Guest/VM so add these extensions to get-reg-list test. Assisted-by: YuanSheng:claude-4.7-opus Co-developed-by: Quan Zhou <zhouquan@iscas.ac.cn> Signed-off-by: Quan Zhou <zhouquan@iscas.ac.cn> Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20260713010302.303278-9-inochiama@gmail.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-07-29RISC-V: KVM: Add support for control-flow integrity FWFT featuresInochi Amaoto2-0/+107
Control-flow integrity is controlled through a WARL field in henvcfg. Expose the feature only if the Zicfilp/Zicfiss is supported for VS-mode. Allow the VMM to block access to the feature by disabling the ISA extension in the guest. Assisted-by: YuanSheng:claude-4.7-opus Co-developed-by: Quan Zhou <zhouquan@iscas.ac.cn> Signed-off-by: Quan Zhou <zhouquan@iscas.ac.cn> Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Link: https://lore.kernel.org/r/20260713010302.303278-8-inochiama@gmail.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-07-29IB/isert: reject login PDUs declaring more data than was receivedYehyeong Lee1-1/+24
isert_login_recv_done() records how many bytes the HCA actually placed in the login buffer, but nothing compares that against the length the login PDU's BHS declares. isert_rx_login_req() copies min(login_req_len, MAX_KEY_VALUE_PAIRS) bytes into login->req_buf, and the login code then reads the declared length back out of that buffer - for the first PDU in iscsi_target_locate_portal(), payload_length = ntoh24(login_req->dlength); tmpbuf = kmemdup_nul(login->req_buf, payload_length, GFP_KERNEL); and for the ones after it in iscsi_decode_text_input(), reached from iscsi_target_do_login(). login->req_buf is a fixed MAX_KEY_VALUE_PAIRS (8192) byte allocation, so an initiator that declares more than it sends reads off the end of it, before authentication and with the length under its control: BUG: KASAN: slab-out-of-bounds in kmemdup_nul+0x43/0x80 Read of size 8193 at addr ffff8881056a8000 by task iscsi_np/167 __asan_memcpy+0x23/0x60 kmemdup_nul+0x43/0x80 iscsi_target_locate_portal+0x48d/0x1180 iscsi_target_login_thread+0x19a9/0x3350 Allocated by task 167: __kmalloc_cache_noprof+0x158/0x370 iscsi_target_login_thread+0x971/0x3350 which belongs to the cache kmalloc-8k of size 8192 allocated 8192-byte region Falsifying the second login PDU instead reaches the other reader, on the same buffer: BUG: KASAN: slab-out-of-bounds in kmemdup_nul+0x43/0x80 Read of size 8193 at addr ffff888104d10000 by task kworker/1:1/50 Workqueue: isert_login_wq iscsi_target_do_login_rx __asan_memcpy+0x23/0x60 kmemdup_nul+0x43/0x80 iscsi_decode_text_input+0xc6/0x11c0 iscsi_target_do_login+0x261/0x1470 iscsi_target_do_login_rx+0x51d/0x7d0 iscsit over TCP is not exposed: iscsit_get_login_rx() validates the declared length with iscsi_target_check_login_request() and then reads exactly that many bytes off the socket, so the declared length governs how much arrives rather than how much is copied out of an already-filled buffer. isert does not call iscsi_target_check_login_request() at all. Reject a login PDU whose declared DataSegmentLength exceeds what was received, in both paths that reach isert_rx_login_req(): isert_get_login_rx() for the first login PDU and isert_login_recv_done() for the ones after it. dlength <= login_req_len is allowed because the received count can include up to three bytes of iSCSI padding. Once the check is in place the copy out can no longer exceed the copy in: the posted login SGE is ISER_RX_PAYLOAD_SIZE, so login_req_len cannot exceed MAX_KEY_VALUE_PAIRS and the min() in isert_rx_login_req() is login_req_len. Like the existing short-PDU check added by 29e7b925ae6d, the reject in isert_login_recv_done() returns without completing login_req_comp, so a malformed subsequent PDU leaves the login to be torn down by the login timer rather than failing immediately. The first-PDU path returns an error and fails straight away. Reproduced on 7.2.0-rc4 with soft-RoCE (rdma_rxe) under KASAN, using an initiator that sends the real key=value payload while declaring 8193 in the BHS, on the first login PDU and on the second in separate runs. The reported read size tracks the declared value exactly; 16384 and 61440 behave the same. Unpatched 3 of 3 runs report on each of the two paths, patched 0 of 3 on both, run alternately in a single session, and a normal login still completes on the patched build. Fixes: b8d26b3be8b3 ("iser-target: Add iSCSI Extensions for RDMA (iSER) target driver") Suggested-by: Leon Romanovsky <leonro@nvidia.com> Signed-off-by: Yehyeong Lee <yhlee@isslab.korea.ac.kr> Link: https://patch.msgid.link/20260726163931.971063-3-yhlee@isslab.korea.ac.kr Signed-off-by: Leon Romanovsky <leon@kernel.org>
2026-07-29IB/isert: reject PDUs declaring more data than was receivedYehyeong Lee1-0/+15
isert_recv_done() hands each received PDU to the opcode handlers without ever looking at wc->byte_len, the number of bytes the HCA actually placed in the receive descriptor. The handlers then copy that many bytes - the data-segment length the initiator declared in the BHS (ntoh24(hdr->dlength), via the derived unsol_data_len / imm_data_len) - out of the fixed-size descriptor: isert_handle_iscsi_dataout(): sg_copy_from_buffer(sg_start, sg_nents, isert_get_data(rx_desc), unsol_data_len); isert_handle_scsi_cmd(): sg_copy_from_buffer(cmd->se_cmd.t_data_sg, sg_nents, isert_get_data(rx_desc), imm_data_len); Because the declared length is never checked against wc->byte_len, an initiator can declare a data segment larger than the bytes it actually sent (and larger than the descriptor) and cause an out-of-bounds read of the receive buffer. Nothing upstream of isert closes this door: - __iscsit_check_dataout_hdr() bounds the inbound payload against conn_ops->MaxXmitDataSegmentLength (MXDSL) - a transmit parameter, used here for the inbound check. - iscsi_set_connection_parameters() sets ops->MaxXmitDataSegmentLength = ops->TargetRecvDataSegmentLength; and TARGETRECVDATASEGMENTLENGTH is absent from the min()-clamp list in iscsi_check_acceptor_state(), so the value the initiator declares is adopted verbatim (type range 512..16777215). The initiator effectively raises its own ceiling. - isert never clamps the negotiated value to its own fixed receive descriptor (ISER_RX_SIZE, 9216 bytes), so the target core's bound and the descriptor size are unrelated. The imm_data_len == data_len path is more than an over-read: it aliases the receive descriptor via sg_set_buf() and passes it to the backend as the data source for the SCSI WRITE, so an over-declared length causes heap contents past the descriptor to be written through the backend to the backing store. The backend is the victim of the oversized scatterlist isert hands it, not the cause; no read-back of the written bytes was demonstrated. Trigger: after login completes (full feature phase), an initiator that has declared a large TargetRecvDataSegmentLength and a FirstBurstLength that permits unsolicited/immediate data sends a PDU whose declared data-segment length exceeds what was received. With KASAN: BUG: KASAN: slab-out-of-bounds in sg_copy_buffer+0x150/0x1c0 Read of size 4096 at addr ffff888109720800 by task kworker/1:0H/25 Workqueue: ib-comp-wq ib_cq_poll_work Call Trace: sg_copy_buffer+0x150/0x1c0 isert_recv_done+0xba6/0x2390 __ib_process_cq+0xe1/0x390 ib_cq_poll_work+0x46/0x150 isert_recv_done+0xba6 resolves to isert_handle_iscsi_dataout() (ib_isert.c:1160), inlined through isert_rx_opcode(). Validate wc->byte_len against the framing in isert_recv_done() before the PDU reaches any handler, and reinstate the connection if it is short. Because the test compares without subtracting the header length, it also rejects PDUs shorter than the iSER and iSCSI headers, which would otherwise be parsed out of stale descriptor contents. The login handler rejects PDUs shorter than ISER_HEADERS_LEN (commit 29e7b925ae6d ("IB/isert: Reject login PDUs shorter than ISER_HEADERS_LEN")) but does not bound the declared length either; that is fixed in the next patch. The data handlers had no length check at all. isert reads the data segment from a fixed offset: isert_get_data() returns the iSER header plus ISER_HEADERS_LEN and makes no adjustment for an AHS. The bytes the handlers touch are therefore exactly [ISER_HEADERS_LEN, ISER_HEADERS_LEN + dlength), and comparing that sum against wc->byte_len bounds precisely the region that is read. An AHS term would only make the test stricter without bounding anything further, and cannot cause a false reject: a PDU carrying an AHS is longer, not shorter. This is a memory-safety fix that verifies the bytes that were actually received; it does not touch RFC 7145 length negotiation and is not the MaxXmitDataSegmentLength negotiation redesign raised in the 2017 "[Query] iSER-Target: QP errors observed on increasing MaxXmitDataSegmentLength" discussion. That redesign is explicitly out of scope here. The patched kernel rejects the malformed DataOut PDU and both immediate-data variants with "PDU declares ... bytes were received" and continues to pass normal traffic with no regression. Reproduced with soft-RoCE (rdma_rxe) and a raw rdma_cm/ibv initiator; no kernel-side test hooks were needed. Fixes: b8d26b3be8b3 ("iser-target: Add iSCSI Extensions for RDMA (iSER) target driver") Signed-off-by: Yehyeong Lee <yhlee@isslab.korea.ac.kr> Link: https://patch.msgid.link/20260726163931.971063-2-yhlee@isslab.korea.ac.kr Signed-off-by: Leon Romanovsky <leon@kernel.org>
2026-07-29RISC-V: KVM: Handle software-check exits for VCPUInochi Amaoto2-0/+12
The extension Zicfiss/Zicfilp introduces a software-check exception to the privilege architecture. Redirect this exception to VS mode when VCPU enable Zicfiss/Zicfilp so the CFI violations in VU/VS could be reported. Also, update kvm_riscv_vcpu_trap_redirect() to forward the SPELP state to the VS mode. Assisted-by: YuanSheng:claude-4.7-opus Co-developed-by: Quan Zhou <zhouquan@iscas.ac.cn> Signed-off-by: Quan Zhou <zhouquan@iscas.ac.cn> Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20260713010302.303278-6-inochiama@gmail.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-07-29media: ipu-bridge: Add upside-down sensor DMI quirk for Samsung Galaxy Book5 Pro 360Mihail Antsev1-0/+8
The Samsung Galaxy Book5 Pro 360 (960QHA) has an upside-down mounted OV02E10 sensor. The 180 degree rotation is reported in neither the SSDB nor the _PLD for the sensor (both report a rotation of 0 degrees), so the image is rendered upside-down in userspace. Add a DMI quirk entry for this laptop so that the sensor fwnode gets a "rotation" property of 180 and userspace (e.g. libcamera) can compensate. Tested on the Galaxy Book5 Pro 360: with the sensor reporting V4L2_CID_CAMERA_SENSOR_ROTATION = 180 (verified with an equivalent local sensor-driver quirk), libcamera renders the image upright. Signed-off-by: Mihail Antsev <mihail.antcev@gmail.com> Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
2026-07-29media: i2c: cvs: Pass link frequency explicitly to csi_set_link_cfg()Laurent Pinchart2-11/+8
The link frequency, retrieved in cvs_csi_enable_streams(), is stored in the icvs structure to then be used right after in csi_set_link_cfg(), called only from the same function. Pass it as a function parameter instead to improve readability. Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Tested-by: Antti Laakso <antti.laakso@linux.intel.com> Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
2026-07-29media: i2c: mt9t112: fix incorrect PTR_ERR() call on non-error pointerUday Khare1-4/+5
In mt9t112_probe(), the clock error check after devm_v4l2_sensor_clk_get() calls PTR_ERR(priv->clk) unconditionally, before testing IS_ERR(). On a successful lookup, priv->clk is a valid pointer and calling PTR_ERR() on it is incorrect API usage. While the comparison against -ENOENT happens to be harmless in practice (valid kernel pointers never fall in the error range), this is still a violation of the IS_ERR()/PTR_ERR() contract that can mislead readers. Restructure the check to guard PTR_ERR() inside IS_ERR(), using the simpler != -ENOENT form to avoid an unnecessary else clause. Signed-off-by: Uday Khare <udaykhare77@gmail.com> Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
2026-07-29media: i2c: ov9282: restore flash duration calculationRichard Leitner1-1/+2
The migration to CCI helpers made V4L2_CID_FLASH_DURATION write the requested duration directly to OV9282_REG_STROBE_FRAME_SPAN, dropping the conversion from microseconds to the register value. This made flash strobes too long and produced overly bright frames. Restore the missing calculation so flash duration is programmed correctly again. Fixes: 273f52f3cbec ("media: i2c: ov9282: Convert to CCI register access helpers") Cc: Xiaolei Wang <xiaolei.wang@windriver.com> Cc: stable@vger.kernel.org Signed-off-by: Richard Leitner <richard.leitner@linux.dev> Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
2026-07-29media: staging/ipu7: fix async notifier leak on init errorCong Nguyen1-0/+1
isys_notifier_init() initialises a v4l2 async notifier and then, for each CSI-2 port, adds a remote sensor subdev to the notifier's waiting_list via v4l2_async_nf_add_fwnode_remote(), which allocates a sensor_async_sd descriptor and takes a fwnode reference. If parsing or adding a later port fails, the code jumps to the "err_parse" label, which only drops the current endpoint fwnode reference and returns, without calling v4l2_async_nf_cleanup(). Any descriptors already added to the notifier for earlier ports are therefore leaked, and the caller's error path does not clean up the notifier either. Call v4l2_async_nf_cleanup() on the error path, matching the cleanup already performed when v4l2_async_nf_register() fails. This is safe as the notifier is always initialised before the loop is entered. Fixes: a516d36bdc3d ("media: staging/ipu7: add IPU7 input system device driver") Signed-off-by: Cong Nguyen <congnt264@gmail.com> Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
2026-07-29media: ov2740: move regmap_config to a static const variableLink Mauve1-4/+6
This one was fully static, so no need to fill it in the register function manually. Signed-off-by: Link Mauve <linkmauve@linkmauve.fr> Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
2026-07-29media: ov2740: define most fields on variable declarationLink Mauve1-14/+13
This also removes initializing reg_write to NULL, which will help with changing its signature in nvmem-provider[1]. Thanks to Sakari Ailus for their suggestion[2]! [1] https://lore.kernel.org/rust-for-linux/20260716142415.28718-1-linkmauve@linkmauve.fr/ [2] https://lore.kernel.org/rust-for-linux/al3sxMUgeK49dwNs@kekkonen.localdomain/ Signed-off-by: Link Mauve <linkmauve@linkmauve.fr> Suggested-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
2026-07-29media: imx219: add test patternsTharit Tangkijwanichakul1-6/+21
Add 5 missing test patterns to complete the available hardware test patterns. The original mapping for color bars and solid color in the menu is preserved to prevent existing userspace application and automated vendor capture tests. The changes were validated on a raspberry pi 5 with an imx219 sensor using v4l2-ctl and rpicam-still. Signed-off-by: Tharit Tangkijwanichakul <tharitt97@gmail.com> Reviewed-by: Jai Luthra <jai.luthra@ideasonboard.com> Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
2026-07-29media: i2c: vd55g1: Fix wrong output FPS valueBenjamin Mugnier1-14/+1
Running the sensor on 10 bits mode resulted in FPS being 25% faster than it should be. This issue did not appear in 8 bits mode. This is mostly noticeable with libcamera as it can set a target FPS value directly. This is caused by the V4L2_CID_PIXEL_RATE control being dynamically changed according to the media bus code, while it should be the same regardless of the code. Since we already compute the pixel_clock, use it directly for V4L2_CID_PIXEL_RATE instead. Suggested-by: Dave Stevenson <dave.stevenson@raspberrypi.com> Signed-off-by: Benjamin Mugnier <benjamin.mugnier@foss.st.com> Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
2026-07-29drm/mediatek: ovl_adaptor: balance component registrationsMyeonghun Pak1-1/+6
The OVL adaptor registers both an aggregate driver for its child devices and a component for the main DRM aggregate. Probe currently ignores an error from registering the child aggregate and leaves that aggregate registered if registering the DRM component fails. The remove callback also leaves the DRM component registered. These imbalances can leave component framework entries referring to a device whose probe failed or whose driver has been detached. The aggregate unbind callback also fails to undo component_bind_all(), leaving its child components marked as bound when the aggregate is removed. Check the aggregate registration result, unwind it when the component registration fails, and unregister the component before the aggregate on remove. Keep runtime PM enabled until both framework registrations have been removed, and unbind all child components from the aggregate unbind callback. Fixes: 453c3364632a ("drm/mediatek: Add ovl_adaptor support for MT8195") Cc: stable@vger.kernel.org # 6.4+ Co-developed-by: Ijae Kim <ae878000@gmail.com> Signed-off-by: Ijae Kim <ae878000@gmail.com> Signed-off-by: Myeonghun Pak <mhun512@gmail.com> Reviewed-by: CK Hu <ck.hu@mediatek.com> Link: https://patchwork.kernel.org/project/linux-mediatek/patch/20260721152242.47138-1-mhun512@gmail.com/ Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
2026-07-29KVM: selftests: Trigger L2->L1 exits stress save+restore and #PF testYosry Ahmed2-4/+45
Extend the testing coverage in L2 by forcing a nested VM-Exit from L2 to L1 right after restore on every other iteration. Forcing a nested VM-Exit while L0 has control (e.g. without explicitly running L2 and making a hypercall) is valuable, as it often happens during live migration (e.g. L1 timer interrupt fires by the time the VM lands on the destination). To force the nested VM-Exit inject a #UD in to the saved vCPU state, and intercept #UD from L1. With this change, the test reliably reproduces the CR2 bug fixed by commit 5c247d08bc81 ("KVM: nSVM: Use vcpu->arch.cr2 when updating vmcb12 on nested #VMEXIT") -- at least on Milan, Genoa, and Turin CPUs. Assisted-by: Gemini:gemini-3.1-pro Signed-off-by: Yosry Ahmed <yosry@kernel.org> Link: https://patch.msgid.link/20260728174232.2423257-14-yosry@kernel.org Signed-off-by: Sean Christopherson <seanjc@google.com>
2026-07-29KVM: selftests: Support running stress save+restore and #PF test in L2Yosry Ahmed1-3/+53
Extend the stress test to allow running the access+#PF code in L2 instead of L1 by adding proper L1 guest code to bootstrap L2. By default, the test runs in L2 after running in L1 if nested is supported. Assisted-by: Gemini:gemini-3.1-pro Signed-off-by: Yosry Ahmed <yosry@kernel.org> Link: https://patch.msgid.link/20260728174232.2423257-13-yosry@kernel.org Signed-off-by: Sean Christopherson <seanjc@google.com>
2026-07-29KVM: selftests: Trigger save+restore randomly in the #PF stress testYosry Ahmed1-7/+49
Instead of an explicit GUEST_SYNC() after each access+#PF, run another thread that keeps sending SIGUSR to the vCPU thread, essentially triggering exits to userspace and save+restore on random points in guest execution. This makes the test a lot more meaningful as it opens the door to exercising race conditions between #PF handling in the guest and save+restore in the host. The signals are ignored using SIG_IGN outside of __vcpu_run() to avoid interrupting other ioctls/sysctls performed by the test. Assisted-by: Gemini:gemini-3.1-pro Signed-off-by: Yosry Ahmed <yosry@kernel.org> Link: https://patch.msgid.link/20260728174232.2423257-12-yosry@kernel.org Signed-off-by: Sean Christopherson <seanjc@google.com>
2026-07-29KVM: selftests: Add basic stress test for save+restore and #PF handlingYosry Ahmed3-0/+174
Add a basic stress test for handling #PFs in a guest while the host is doing save+restore cycles. The guest periodically accesses non-present memory causing a #PF, and the #PF handler walks the page tables and updates the PTE to be present, like a proper #PF handler. After every access (and #PF), the guest triggers a sync and the test performs save+restore of the VM. This is not very meaningful as save+restore are performed after the access and #PF handling complete, but following changes will change that. Assisted-by: Gemini:gemini-3.1-pro Signed-off-by: Yosry Ahmed <yosry@kernel.org> Link: https://patch.msgid.link/20260728174232.2423257-11-yosry@kernel.org Signed-off-by: Sean Christopherson <seanjc@google.com>
2026-07-29KVM: selftests: Do not intercept #PF by default in nVMX testsYosry Ahmed1-1/+1
init_vmcs_control_fields() sets PFEC_MASK and PFEC_MATCH so that they never match, which reverses the meaning of the PF_VECTOR bit in EXCEPTION_BITMAP (which is zeroed), effectively enabling #PF interception by default. The relevant part of the SDM describes this: When a page fault occurs, a processor consults (1) bit 14 of the exception bitmap; (2) the error code produced with the page fault [PFEC]; (3) the page-fault error-code mask field [PFEC_MASK]; and (4) the page-fault error-code match field [PFEC_MATCH]. It checks if PFEC & PFEC_MASK = PFEC_MATCH. If there is equality, the specification of bit 14 in the exception bitmap is followed (for example, a VM exit occurs if that bit is set). If there is inequality, the meaning of that bit is reversed (for example, a VM exit occurs if that bit is clear). Clear PFEC_MATCH such that there is equality, and the #PF bit in the exception bitmap is followed, so that #PFs are not intercepted by default, same as every other exception. This also allows tests to set the #PF bit in the exception bitmap if they want to intercept #PFs, without having to muck with the PFEC_{MASK,MATCH} fields. Suggested-by: Sean Christopherson <seanjc@google.com> Signed-off-by: Yosry Ahmed <yosry@kernel.org> Link: https://patch.msgid.link/20260728174232.2423257-10-yosry@kernel.org Signed-off-by: Sean Christopherson <seanjc@google.com>
2026-07-29drm/mediatek: mtk_dsi: Enable HS clock only at pre-enableAngeloGioacchino Del Regno1-2/+3
Commit 76255024cadb ("drm/mediatek: mtk_dsi: enable hs clock during pre-enable") rightfully moves the HS clock enablement to before atomic_enable(), but it's moving it to mtk_dsi_poweron(), which is not only called in the .atomic_pre_enable() callback for the DRM bridge, but also in the MediaTek DRM's .ddp_start() callback, which happens way before the bridge ones. The HS clock enablement should be done at just the right time, otherwise some bridge chips (or some Display Driver ICs) may not work correctly: this is seen at least with a Parade DSI to eDP bridge (PS8640) on the MT8173 Elm Chromebook. This resolves a regression that was seen on the aforementioned machine, which was happening only after a suspend-resume cycle. Cc: <stable@vger.kernel.org> # 7.1.x Fixes: 76255024cadb ("drm/mediatek: mtk_dsi: enable hs clock during pre-enable") Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Tested-by: Adam Thiede <me@adamthiede.com> Reviewed-by: CK Hu <ck.hu@mediatek.com> Link: https://patchwork.kernel.org/project/linux-mediatek/patch/20260728153145.578404-1-angelogioacchino.delregno@collabora.com/ Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
2026-07-29KVM: selftests: Expose PTE masks to guests as part of an MMUYosry Ahmed2-0/+13
Expose a guest_mmu to the guest to allow guest code to use the PTE masks for page table manipulation. Since guest page tables are not mapped in the guest by default, zero the PGD in guest_mmu in an attempt to make it more difficult for new tests to shoot themselves in the foot and assume that page tables can be immediately used by guest code. Ultimately, guest code can read CR3 any way, so guest_mmu.pgd doesn't add a lot of value. Suggested-by: Sean Christopherson <seanjc@google.com> Signed-off-by: Yosry Ahmed <yosry@kernel.org> Link: https://patch.msgid.link/20260728174232.2423257-9-yosry@kernel.org Signed-off-by: Sean Christopherson <seanjc@google.com>
2026-07-29KVM: selftests: Add a blank line before logging assertion failuresYosry Ahmed1-1/+1
Add a blank line for visual separation, which is especially useful for tests that use carriage returns for same-line printing, in case a failure occurs before a blank line is ever logged by the test. Suggested-by: Sean Christopherson <seanjc@google.com> Signed-off-by: Yosry Ahmed <yosry@kernel.org> Link: https://patch.msgid.link/20260728174232.2423257-8-yosry@kernel.org Signed-off-by: Sean Christopherson <seanjc@google.com>
2026-07-29KVM: selftests: Drop HORRIFIC_L2_UCALL_CLOBBER_HACKYosry Ahmed1-30/+2
Now that nVMX test codes preserves GPRs across nested VM-Exits (specifically RBP, RDX, and RDI among others), drop the ucall-specific hack to avoid clobbering these registers. Assisted-by: Gemini:gemini-3.1-pro Signed-off-by: Yosry Ahmed <yosry@kernel.org> Link: https://patch.msgid.link/20260728174232.2423257-7-yosry@kernel.org Signed-off-by: Sean Christopherson <seanjc@google.com>
2026-07-29KVM: selftests: Reuse GPR switching logic for nVMXYosry Ahmed2-66/+49
Reuse the GPR switching logic for nVMX by defining VMX_SWITCH_GPRS_ASM, which is essentially the same as SVM_SWITCH_GPRS_ASM but also switches RAX and doesn't switch RFLAGS, replacing the push/pop of a subset of the registers. The long clobber list of registers is no longer needed as registers are saved and restored appropriately (and not clobbered by L2). Define VMX_SWITCH_GPRS_ASM before including evmcs.h, such that it can be used by evmcs_vmlaunch() and evmcs_vmresume(). This replaces the apparently thread-safe push/pop sequence with the global GPR switching logic used by SVM, which isn't thread-safe at all. However this is still an improvement because: - The VMX logic is half-baked and prompts the UCALL clobber hack as it doesn't properly save/restore everything. Reusing the GPR switching logic used by SVM allows for dropping that hack. - Hitting a problem due to half-baked GPR save/restore logic is arguably more likely than thread-safety. Evidently, adding more involved stress tests fails on VMX with the existing push/pop sequence. OTOH, there are no known failures on SVM due to lack of thread-safety fo save/restore. Only one test currently uses more than one vCPU with nested (the memstress test). The logical next step is to move the guest_regs to be per-vCPU, making it thread-safe for both VMX and SVM in a proper way. Assisted-by: Gemini:gemini-3.1-pro Signed-off-by: Yosry Ahmed <yosry@kernel.org> Link: https://patch.msgid.link/20260728174232.2423257-6-yosry@kernel.org Signed-off-by: Sean Christopherson <seanjc@google.com>
2026-07-29KVM: selftests: Handle rflags save/restore for SVM in guest_regsYosry Ahmed2-5/+5
Instead of handling rflags separately, add it to guest_regs. No functional change intended. Assisted-by: Gemini:Gemini-Next Signed-off-by: Yosry Ahmed <yosry@kernel.org> Link: https://patch.msgid.link/20260728174232.2423257-5-yosry@kernel.org Signed-off-by: Sean Christopherson <seanjc@google.com>
2026-07-29KVM: selftests: Rework GPR registers switching for SVM (and fix offsets)Yosry Ahmed3-28/+54
The assembly code defined by SAVE_GPR_C uses the wrong offsets for some registers in guest_regs. For example, the offset of RCX should be 0x08 not 0x10. Also, the last offset in the struct (R15) is 0x78, not 0x80, so the code actually saves and restore beyond the end of gpr64_regs. Eliminate hardcoded offsets by dynamically generating offsets using offset_of() and using macros to pass the offsets to assembly as asm constraints. To avoid register conflicts in inline assembly (since almost all GPRs are context-switched), access guest_regs via absolute symbol addressing (guest_regs + offset) rather than using a base register which could get overwritten mid-assembly. While at it, rename SAVE_GPR_C and LOAD_GPR_C to a single macro, SVM_SWITCH_GPRS_ASM, rename gpr64_regs to guest_regs, and expose it in processor.h (in preparation for reusing it for VMX). Assisted-by: Gemini:Gemini-Next Signed-off-by: Yosry Ahmed <yosry@kernel.org> Link: https://patch.msgid.link/20260728174232.2423257-4-yosry@kernel.org Signed-off-by: Sean Christopherson <seanjc@google.com>
2026-07-29KVM: selftests: Fix RAX and RFLAGS VMCB offsets when running L2Yosry Ahmed1-8/+11
The offsets used (0x170 and 0x1f8) are offsets within vmcb_save_area, not vmcb. The correct offsets should include the base of vmcb_save_area within vmcb (which is 0x400 -- so 0x570 and 0x5f8). Instead of just correcting the offsets, use vmcb->save.rax and vmcb->save.rflags as parameters to the asm block and avoid hardcoding offsets completely. While at it, also use guest_regs.rax directly instead of assuming it's at offset 0 of guest_regs. Note: "+m" must be used for vmcb_rax and vmcb_rflags, as caching those fields in registers would be wrong as the underlying KVM will update them in memory. The same problem was recently fixed (differently) for kvm-unit-tests [1]. [1]https://lore.kernel.org/all/20260521092311.86030-1-pbonzini@redhat.com/ Reported-by: Sashiko <sashiko-bot@kernel.org> Closes: https://sashiko.dev/#/patchset/20260518202514.2037078-1-yosry%40kernel.org?part=1 Signed-off-by: Yosry Ahmed <yosry@kernel.org> Link: https://patch.msgid.link/20260728174232.2423257-3-yosry@kernel.org Signed-off-by: Sean Christopherson <seanjc@google.com>
2026-07-29KVM: selftests: Use __stringify() instead of custom XSTR() macrosYosry Ahmed4-9/+3
Drop the custom defined XSTR() macros in KVM selftests and use __stringify() instead. Include stringify.h in test_util.h to make it available for all tests instead of including it in all the tests that need it, as more tests will start using it. No functional change intended. Signed-off-by: Yosry Ahmed <yosry@kernel.org> Link: https://patch.msgid.link/20260728174232.2423257-2-yosry@kernel.org Signed-off-by: Sean Christopherson <seanjc@google.com>
2026-07-29KVM: x86/mmu: Use CMPXCHG when clearing Accessed bit in the shadow MMUSean Christopherson1-13/+14
Use CMPXCHG instead of clear_bit(), which currently emits a LOCK BTR since the to-be-cleared bit isn't a compile-time constant, when aging SPTEs in the shadow MMU to align with the approach taken by the TDP MMU, and because using CMPXCHG is far more robust against bugs in KVM. E.g. if the SPTE is somehow no longer an SPTE due to a KVM bug, CMPXCHG will fail gracefully, whereas clear_bit() would potentially corrupt/clobber memory. Clearing the Accessed bit without atomically ensuring the SPTE is still the old SPTE is "fine", as holding the rmap's lock ensures zapping the old SPTE can't fully complete, which in turn ensures a new, different SPTE can't be installed. But that chain of logic isn't exactly obvious, and there's zero reason to avoid CMPXCHG as its cost on modern hardware is within ~1-2 uops of LOCK BTR (and may even be cheaper on some microarchitectures). Doing a 64-bit CMPXCHG on 32-bit kernels does require a more expensive CMPXCHG8B, but 32-bit KVM is all but dead at this point. Cc: James Houghton <jthoughton@google.com> Reviewed-by: Kai Huang <kai.huang@intel.com> Reviewed-by: James Houghton <jthoughton@google.com> Link: https://patch.msgid.link/20260728002236.869865-3-seanjc@google.com Signed-off-by: Sean Christopherson <seanjc@google.com>
2026-07-29KVM: x86/mmu: Use CMPXCHG when clearing Accessed bit in TDP MMUSean Christopherson2-11/+16
Use LOCK CMPXCHG instead of LOCK AND to clear the Accessed bit when aging SPTEs in the TDP MMU, as doing a LOCK AND can corrupt a FROZEN SPTE and allow a third CPU to effectively overwrite the FROZEN SPTE. As pointed out by AI of some kind, because the magic FROZEN_SPTE value is a "full" SPTE, not a single bit, and includes the Accessed bit, clearing the Accessed bit in a FROZEN SPTE will result in is_frozen_spte() getting a false negative. E.g. if CPU0 freezes an SPTE, and CPU1 clears the Accessed bit in the frozen SPTE, then CPU2 could come along and overwrite the frozen SPTE with a shadow-present SPTE. Thankfully, the false negative is largely benign, because outside of TDX, which doesn't support aging, KVM only freezes leaf SPTEs when removing an upper level shadow page. So while KVM could clobber a frozen SPTE back to a shadow-present SPTE, and could even use the new SPTE, the subsequent TLB flush will make the orphaned, shadow-present SPTE unreachable. Failure to ever zap the orphaned leaf SPTE would show up in KVM's stats, but otherwise is benign (because KVM no longer keeps an elevated refcount for leaf SPTEs). Opportunistically add a comment to warn future developers away from using kvm_tdp_mmu_write_spte_atomic() and tdp_mmu_clear_spte_bits_atomic(), as they are generally unsafe. Keep the helpers, e.g. instead of open-coding the atomic64_fetch_and() in tdp_mmu_clear_spte_bits(), as scary warnings usually are more effective deterrent against recidivism than removal of the dangerous code. Alternatively, KVM could use different bits for the magic FROZEN_SPTE value, e.g. setting the Dirty bits (with effective IPAT and Global aliases) would likely be "ok", as IPAT/Global are extremely unlikely to be cleared without doing a full SPTE write, and KVM's clearing of Dirty bits shares logic with Write-Protection, which must do a full SPTE write (via cmpxchg64() in the TDP MMU) to ensure KVM isn't clobbering state. But there is zero reason to carry that risk (beyond stubbornness in wanting to preserve a "cute" idea), as the cost of LOCK CMPXCHG and LOCK AND are within 1-2 uops of each other on modern hardware. Fixes: b146a9b34aed ("KVM: x86/mmu: Age TDP MMU SPTEs without holding mmu_lock") Cc: stable@vger.kernel.org Reviewed-by: Kai Huang <kai.huang@intel.com> Reviewed-by: James Houghton <jthoughton@google.com> Link: https://patch.msgid.link/20260728002236.869865-2-seanjc@google.com Signed-off-by: Sean Christopherson <seanjc@google.com>
2026-07-29RISC-V: KVM: Add ssp context save/restoreInochi Amaoto4-2/+88
Add ssp context save/restore for guest VCPUs and also add it to the ONE_REG interface to allow its access from user space. Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20260713010302.303278-5-inochiama@gmail.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-07-29RISC-V: KVM: Allow Zicfiss/Zicfilp extensions for Guest/VMInochi Amaoto2-0/+4
Extend the KVM ISA extension array to allow KVM userspace to detect and enable Zicfiss/Zicfilp extensions for Guest/VM. Assisted-by: YuanSheng:claude-4.7-opus Co-developed-by: Quan Zhou <zhouquan@iscas.ac.cn> Signed-off-by: Quan Zhou <zhouquan@iscas.ac.cn> Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20260713010302.303278-4-inochiama@gmail.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-07-29KVM: riscv: selftests: add Svadu FWFT extension to get-reg-list testInochi Amaoto1-0/+21
The KVM RISC-V allows Svadu FWFT for Guest/VM so add this extension to get-reg-list test. Assisted-by: YuanSheng:claude-4.7-opus Co-developed-by: Quan Zhou <zhouquan@iscas.ac.cn> Signed-off-by: Quan Zhou <zhouquan@iscas.ac.cn> Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20260713010302.303278-3-inochiama@gmail.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-07-29RISC-V: KVM: Add support for Svadu FWFT featuresInochi Amaoto2-0/+74
Hardware updating of PTE A/D bits is controlled through ADUE bit in henvcfg Expose the feature only if both Svadu and Svade are supported for VS-mode. Allow the VMM to enable/disable this feature by change the ISA extension state in the guest. Assisted-by: YuanSheng:claude-4.7-opus Co-developed-by: Quan Zhou <zhouquan@iscas.ac.cn> Signed-off-by: Quan Zhou <zhouquan@iscas.ac.cn> Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20260713010302.303278-2-inochiama@gmail.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-07-29MAINTAINERS: Demote myself to reviewerMichael Ellerman1-1/+1
I haven't been active enough lately to warrant an M: maintainer entry, demote me to reviewer. Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Signed-off-by: Madhavan Srinivasan <maddy@linux.ibm.com> Link: https://patch.msgid.link/87y0hspx0u.fsf@mpe.ellerman.id.au