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WireGuard for the Linux kernel
Jason A. Donenfeld
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riscv
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cpu.c
Age
Commit message (
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Author
Files
Lines
2019-10-28
RISC-V: Remove unsupported isa string info print
Atish Patra
1
-42
/
+3
2019-06-05
treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286
Thomas Gleixner
1
-9
/
+1
2019-04-30
RISC-V: Add RISC-V specific arch_match_cpu_phys_id
Atish Patra
1
-2
/
+1
2019-03-04
RISC-V: Remove NR_CPUs check during hartid search from DT
Atish Patra
1
-4
/
+0
2019-02-11
riscv: treat cpu devicetree nodes without status as enabled
Johan Hovold
1
-7
/
+3
2019-02-11
riscv: fix riscv_of_processor_hartid() comment
Johan Hovold
1
-9
/
+9
2019-02-11
riscv: add missing newlines to printk messages
Johan Hovold
1
-1
/
+1
2018-12-21
RISC-V: Fix of_node_* refcount
Atish Patra
1
-0
/
+1
2018-11-20
RISC-V: recognize S/U mode bits in print_isa
Patrick Stählin
1
-3
/
+6
2018-10-22
RISC-V: Show CPU ID and Hart ID separately in /proc/cpuinfo
Anup Patel
1
-4
/
+6
2018-10-22
RISC-V: Use Linux logical CPU number instead of hartid
Atish Patra
1
-3
/
+5
2018-10-22
RISC-V: Rename riscv_of_processor_hart to riscv_of_processor_hartid
Palmer Dabbelt
1
-2
/
+5
2018-10-22
RISC-V: Filter ISA and MMU values in cpuinfo
Palmer Dabbelt
1
-7
/
+61
2017-09-26
RISC-V: Init and Halt Code
Palmer Dabbelt
1
-0
/
+108