Age | Commit message (Expand) | Author | Files | Lines |
---|---|---|---|---|
2019-05-16 | RISC-V: Access CSRs using CSR numbers | 1 | -11/+11 | |
2019-01-23 | RISC-V: Add _TIF_NEED_RESCHED check for kernel thread when CONFIG_PREEMPT=y | 1 | -1/+17 | |
2019-01-07 | riscv: add audit support | 1 | -2/+2 | |
2018-10-22 | RISC-V: SMP cleanup and new features | 1 | -1/+0 | |
2018-10-22 | RISC-V: No need to pass scause as arg to do_IRQ() | 1 | -1/+0 | |
2018-10-22 | Extract FPU context operations from entry.S | 1 | -87/+0 | |
2018-08-13 | RISC-V: implement low-level interrupt handling | 1 | -2/+2 | |
2018-03-14 | RISC-V: Move to the new GENERIC_IRQ_MULTI_HANDLER handler | 1 | -4/+3 | |
2018-02-20 | RISC-V: Enable IRQ during exception handling | 1 | -2/+3 | |
2018-01-30 | riscv: disable SUM in the exception handler | 1 | -3/+6 | |
2018-01-07 | riscv: rename SR_* constants to match the spec | 1 | -4/+4 | |
2017-09-26 | RISC-V: Task implementation | 1 | -0/+464 |