| Age | Commit message (Expand) | Author | Files | Lines |
|---|---|---|---|---|
| 2020-03-24 | clk: sprd: add gate for pll clocks |   Xiaolong Zhang | 1 | -0/+17 |
| 2017-12-21 | clk: sprd: add gate clock support |   Chunyan Zhang | 1 | -0/+111 |
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index : wireguard-linux | |
| WireGuard for the Linux kernel | Jason A. Donenfeld |
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