index
:
wireguard-linux
backport-5.4.y
davem/net
davem/net-next
devel
gregkh/stable-5.4.y
jd/bump-compilers
jd/deferred-aip-removal
jd/new-archs
jd/orphan-parallel
jd/rcu-barrier
jd/shorter-socket-lock
jd/unified-crypt-queue
jd/xdp-l3
stable
update-toolchain
WireGuard for the Linux kernel
Jason A. Donenfeld
about
summary
refs
log
tree
commit
diff
stats
homepage
log msg
author
committer
range
path:
root
/
drivers
/
clk
/
tegra
/
clk-divider.c
(
follow
)
Age
Commit message (
Expand
)
Author
Files
Lines
2020-01-10
clk: tegra: divider: Check UART's divider enable-bit state on rate's recalculation
Dmitry Osipenko
1
-2
/
+7
2019-11-11
clk: tegra: divider: Save and restore divider rate
Sowjanya Komatineni
1
-0
/
+11
2019-05-30
treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 201
Thomas Gleixner
1
-12
/
+1
2019-04-25
clk: tegra: divider: Mark Memory Controller clock as read-only
Dmitry Osipenko
1
-1
/
+2
2018-08-14
Merge branches 'clk-imx6-ocram', 'clk-missing-put', 'clk-tegra-sdmmc-jitter', 'clk-allwinner' and 'clk-uniphier' into clk-next
Stephen Boyd
1
-25
/
+5
2018-07-25
clk: tegra: Refactor fractional divider calculation
Peter De Schrijver
1
-25
/
+5
2018-07-08
clk: tegra: Mark Memory Controller clock as critical
Dmitry Osipenko
1
-2
/
+3
2015-11-16
tegra/clk-divider: fix wrong do_div() usage
Nicolas Pitre
1
-2
/
+2
2015-07-20
clk: tegra: Properly include clk.h
Stephen Boyd
1
-1
/
+0
2014-11-26
clk: tegra: Implement memory-controller clock
Thierry Reding
1
-0
/
+13
2014-02-17
clk: tegra: use max divider if divider overflows
Andrew Bresticker
1
-1
/
+1
2013-01-28
clk: tegra: add Tegra specific clocks
Prashant Gaikwad
1
-0
/
+187