aboutsummaryrefslogtreecommitdiffstatshomepage
path: root/drivers/clk (follow)
AgeCommit message (Expand)AuthorFilesLines
2022-05-10clk: samsung: exynosautov9: add cmu_core clock supportChanho Park1-0/+92
2022-05-10clk: samsung: add top clock support for Exynos Auto v9 SoCChanho Park2-0/+959
2022-05-07ARM: pxa: move clk register definitions to driverArnd Bergmann6-49/+196
2022-05-07ARM: pxa: move smemc register access from clk to platformArnd Bergmann5-63/+15
2022-05-07cpufreq: pxa3: move clk register access to clk driverArnd Bergmann1-0/+16
2022-05-06clk: sunxi-ng: h616: Add PLL derived 32KHz clockAndre Przywara2-1/+9
2022-05-06clk: sunxi-ng: h6-r: Add RTC gate clockAndre Przywara2-1/+6
2022-05-06clk: tegra: Update kerneldoc to match prototypesThierry Reding1-4/+4
2022-05-06clk: renesas: r9a09g011: Add eth clock and reset entriesPhil Edworthy1-5/+9
2022-05-06clk: renesas: Add RZ/V2M support using the rzg2l driverPhil Edworthy5-0/+181
2022-05-05clk: qcom: gcc-msm8976: Add modem resetAdam Skladowski1-0/+1
2022-05-05clk: qcom: gcc-msm8976: Set floor ops for SDCCAdam Skladowski1-3/+3
2022-05-05clk: renesas: rzg2l: Add support for RZ/V2M reset monitor regPhil Edworthy2-3/+17
2022-05-05clk: renesas: rzg2l: Make use of CLK_MON registers optionalPhil Edworthy4-1/+16
2022-05-05clk: renesas: rzg2l: Set HIWORD mask for all mux and dividersPhil Edworthy3-31/+19
2022-05-05clk: renesas: rzg2l: Add read only versions of the clk macrosPhil Edworthy3-6/+12
2022-05-05clk: renesas: rzg2l: Move the DEF_MUX array size calc into the macroPhil Edworthy3-22/+19
2022-05-05clk: renesas: r9a07g044: Fix OSTM1 module clock nameGeert Uytterhoeven1-1/+1
2022-05-05clk: renesas: r9a07g043: Add clock and reset entries for ADCBiju Das1-0/+6
2022-05-05clk: renesas: r9a07g043: Add TSU clock and reset entryBiju Das1-0/+6
2022-05-05clk: renesas: r9a07g043: Add RSPI clock and reset entriesBiju Das1-0/+9
2022-05-05clk: renesas: r9a07g043: Add clock and reset entries for SPI Multi I/O Bus ControllerBiju Das1-0/+18
2022-05-05clk: renesas: r9a07g044: Add DSI clock and reset entriesBiju Das1-1/+16
2022-05-05clk: renesas: r9a07g044: Add LCDC clock and reset entriesBiju Das1-1/+8
2022-05-05clk: renesas: r9a07g044: Add M4 Clock supportBiju Das1-1/+18
2022-05-05clk: renesas: r9a07g044: Add M3 Clock supportBiju Das1-1/+4
2022-05-05clk: renesas: r9a07g044: Add {M2, M2_DIV2} Clocks supportBiju Das1-1/+4
2022-05-05clk: renesas: r9a07g044: Add M1 clock supportBiju Das1-1/+10
2022-05-05clk: renesas: rzg2l: Add DSI divider clk supportBiju Das2-0/+136
2022-05-05clk: renesas: rzg2l: Add PLL5_4 clk mux supportBiju Das2-0/+103
2022-05-05clk: renesas: rzg2l: Add FOUTPOSTDIV clk supportBiju Das2-0/+235
2022-05-04clk: tegra: Replace .round_rate() with .determine_rate()Rajkumar Kasirajan1-5/+10
2022-05-04clk: tegra: Register clocks from root to leafTimo Alho1-16/+56
2022-05-04clk: tegra: Add missing reset deassertionDiogo Ivo1-0/+12
2022-05-03clk: rockchip: Mark hclk_vo as critical on rk3568Sascha Hauer1-0/+1
2022-05-02Merge 5.18-rc5 into driver-core-nextGreg Kroah-Hartman4-32/+169
2022-05-02clk: imx8mp: add clkout1/2 supportLucas Stach1-0/+14
2022-05-02clk: imx: scu: Use pm_runtime_resume_and_get to fix pm_runtime_get_sync() usageMiaoqian Lin1-1/+1
2022-04-29clk: renesas: cpg-mssr: Add support for R-Car V4HYoshihiro Shimoda5-0/+231
2022-04-29clk: renesas: rcar-gen4: Add CLK_TYPE_GEN4_PLL4Yoshihiro Shimoda4-16/+24
2022-04-28clk: qcom: smd: Update MSM8976 RPM clocks.Adam Skladowski1-4/+4
2022-04-28clk: renesas: r9a07g043: Add WDT clock and reset entriesBiju Das1-0/+10
2022-04-28clk: renesas: r9a07g043: Add OSTM clock and reset entriesBiju Das1-0/+9
2022-04-28clk: renesas: r9a07g043: Add clock and reset entries for CANFDBiju Das1-0/+5
2022-04-28clk: renesas: r9a07g043: Add USB clocks/resetsBiju Das1-0/+12
2022-04-28clk: renesas: r9a07g043: Add SSIF-2 clock and reset entriesBiju Das1-0/+20
2022-04-28clk: renesas: r9a07g043: Add I2C clocks/resetsBiju Das1-0/+12
2022-04-28clk: renesas: r9a06g032: Fix the RTC hclock descriptionMiquel Raynal1-1/+1
2022-04-26clk: en7523: fix wrong pointer check in en7523_clk_probe()Yang Yingliang1-1/+1
2022-04-25clk: mediatek: Add MT8186 ipesys clock supportChun-Jie Chen2-1/+56